1. CELeSTA CERN LATCHUP STUDENT SATELLITE TEST BOARD DEVELOPMENT AND CHARM PRELIMINARY RESULTS Raffaello Secondo ESA/ESTEC CERN Visit - DECEMBER 9 th 2014

2. Overview RadMON V6:  Architecture The CELESTA Test Board V1:  PCB concept and description.  Architecture details. CHARM facility  Test zone  Installation of the Setup  Board interface Preliminary Results  TID  HEH Fluence Calculation  SEL Conclusions and Future Work 1/16 ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

3. RadMon V6 – Main Architecture 2/16 ACTEL FPGA FielDrive Sensor ADC Monitoring ADC Conditioning RADFETs: 100 nm 400 nm PIN Diodes Temperature SRAMs SensorBoard 3V3 and 1V5 voltage regulators 8.5V 18V, -5V, 5V, VMEM PowerBoard MainBoard Three Modules Communication via NanoFIP Network Installation in the SPS Tunnel, PS and PSB Injectors. CHARM and ALICE. ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

4. RadMon V6 – Top View 3/16 TID Measurement Displacement Damage (P-i-n Diodes) Two Memory Banks: Cypress and Toshiba SRAM Withstand up to 200 Gy (ADC is the bottleneck) Connection to Deported Module ALL ICs previously tested at PSI. SRAM BANK 1 SRAM BANK 2 RADFETS P-i-n Diodes Connection Deported Module ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

5. The CELESTA Test Board V1 4/16 SEU: Cypress CY62157EV. Dose: Tyndall RadFet 100 nm. SEL: Brilliance BS62LV1600EIP. Latchup Detection via 16 bit ADC. Board Dimensions: 13.5cm x 10cm. Communication via UART RS422, using MODBUS protocol. All ICs on Board have been tested at PSI as on the RadMON. Timings: SRAM + Radfet scanned every Two minutes. ADC sampling period 1ms. RADFET BRILLIANCE CYPRESS ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

6. The Test Board – Architecture Details 5/16 Dose Measurement SEL Detection SEU/MBU Counting To ADC ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

7. CHARM Test Area 6/16 ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

8. Test Setup 7/16 Setup in the Lab: Two Power Supplies. Conversion RS422 to RS232. Voltage levels take into account the Maximum Voltages to be applied on the operational amplifiers. ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

9. Setup in the Test Area 8/16 Two Boards Tested. RadMON V6 + Deported Module in the same Test Location. ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

10. Setup in the Test Area 9/16 Test Locations ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

11. Acquisition Software 10/16 Remote Control of SEL Threshold. Radfet Sweep Time 100 ms. ADC period = 1 ms. Acquisition Period = 50 ms. Temperature Sensor on Board.

12. Preliminary Test Results – TID 11/16 Board 0001 placed on 24/11/2014 - Board 0002 placed 1/12/2014 Board 0001

13. Preliminary Test Results – TID The Satellite temperature will be needed to compensate temperature effects in post processing. 12/16

14. Preliminary Test Results – SEUs and MBUs 13/16 MBUs and SEUs are stored in different dedicated registers. ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO Board 0001

15. Preliminary Test Results – SEUs Analysis 14/16 The cross section for the used lot of Cypress SRAM was previously measured at PSI: σ = 3. 3·10 -13 cm 2 /bit SEUs = 480000. Size = 8*1024*1024  fluence = 1.7 ·10 11 HEH/cm 2 Given the flux at position 4 as 3.5 ·10 9 HEH/cm 2 ·h : Expected result from FLUKA  fluence = 1.47·10 11 HEH/cm 2 ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO

16. Preliminary Test Results – SELs Latchup Threshold set to 15 mA. ADC ran with 1 ms sampling period. Waiting time before Memory deactivation = 2 ms. 15/16 ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO Sampling Period = 20 ms. Board 0002

17. Conclusions and Future Work 16/16 ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO CELESTA TestBoard  Developed from RadMON V6 concept, for Cubesat Missions.  First prototype Board, moving towards the final PCB.  Measurement of TID, HEH fluence and evaluation of SELs. CHARM facility  Representative Space-Like Environment, used to characterize the Board.  First tests started in late November. Preliminary Results  Comparison with FLUKA.  The Radfet Voltage Analysis need to take Temperature into account.  Micro-Latchups show up from the current plot. Hardware Modifications and Improvements  Memory candidates for SEL. SEL detection using a comparator circuit.  TID measurement (other RadFet options, FGDOS?)  Towards a Final Version of the Board (Power, Dimensions, etc…)

18. Thanks ESA/ESTEC CERN VISIT - DECEMBER 9 TH 2014 RAFFAELLO SECONDO