1. EE544/AEEE561 – Advanced Digital Systems Design Dr. Konstantinos Tatas com.tk@fit.ac.cy http://staff.fit.ac.cy/com.tk

2. Outcomes Understand all steps in the digital system design and implementation process. design digital systems using Hardware Description Languages Identify the available design, synthesis and implementation options and trade-offs between performance, area and power consumption develop testbenches to verify their designs Identify and resolve possible metastability and synchronization issues in digital design Incorporate design reuse practices into their designs Use EDA tools to implement digital systems in FPGA technology Keep up with current developments in digital design methodologies and tools

3. Course Outline Combinational and sequential design practices – State machines, Synchronous and asynchronous design. Synchronous Design Methodology – Clock skew – Asynchronous inputs – Clock Gating - Metastability – Reliable Synchronization of high-speed data transfers Design for performance, design for area, design for low power consumption RTL design using Hardware Description Languages – Verilog Digital system verification – Simulation (event- based/cycle-based/transaction-based/emulation/AMS simulation) – Equivalence checking – Static timing verification – Rapid prototyping RTL Synthesis for ASIC and FPGAs - RTL coding practices for synthesis Hardware accelerators – IP block design for reuse Testing and Design for Testability (DFT) fundamentals – Built-In Self-Test (BIST)

4. Textbooks and References J. F. Wakerly, Digital Design: Principles and Practices, Prentice Hall, 2003. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL”, Prentice Hall, 2004 Michael Keating, Russell John Rickford, Pierre Bricaud, “Reuse Methodology Manual for System-On-A-Chip Designs”, Springer, 2006Michael KeatingRussell John Rickford Pierre Bricaud

5. Assessment Exam: 40% Assignment 1: Paper writing/review (25%) Assignment 2: Group project (25%) Test: 10%

6. Weekly Breakdown Week 1: Digital Revision Week 2: Synchronous Design Week 3: Design flow – Paper review assignment Week 4: Verilog Week 5: Verilog Week 6: Verilog /paper review presentation Week 7: Verification Week 8: Test Week 9: Logic Synthesis/Design for reuse Week 10: Assignment/Group project specifications Week 11: Assignment/Group project review – Case study part 1 Week 12: Assignment/Group project review – Case study part 2 Week 13: Assignment/Group project assessment - Revision

7. The Binary Numbering System Digital systems and computers use the Binary system because it has only two states (0 and 1) A number in the Binary system is expressed by the following expression: Examples: (1011) 2 = (1 X 2 3 )+(0 X 2 2 )+(1 X 2 1 ) +(1 X 2 0 ) = 8+0+2+1= (11) 10 (10110) 2 = (1 X 2 4 )+(0 X 2 3 )+(1 X 2 2 ) +(1 X 2 1 ) +(0 X 2 0 ) = 16+0+4+2+0= (22) 10 (101100) 2 =(1 X 2 5 )+(0 X 2 4 )+(1 X 2 3 )+(1 X 2 2 )+(0 X 2 1 )+(0 X 2 0 )=32+0+8+4+0+0= (44) 10 (d n d n-1 …d 1 d 0 ) 2 = (d n X 2 n )+ (d n-1 X 2 n-1 ) + …+ (d 1 X 2 1 ) +( d 0 X 2 0 ) Where d = {0,1}

8. The Binary Numbering System (Cont.) A binary digit is called the BIT (BInary digiT). A group of eight bits is called the BYTE. The leftmost bit of a number is called the Most Significant Bit (MSB). The rightmost bit of a number is called the Least Significant Bit (LSB). A binary system with N bits can represent the numbers from 0 to 2 N -1. In a binary system with N digits there are 2 N different combinations. A binary number is multiplied by two, if we append a zero at the LSB. Prefixes in the binary system: 2 10 = 1,024 = 1K (Kilo) 2 20 = 1,024 X 1,024 = 1,048,576 = 1M (Mega) 2 30 = 1G (Giga) 2 40 = 1T (Tera) Powers of 2: 2 0 = 1 2 1 = 2 2 2 = 4 2 3 = 8 2 4 = 16 2 5 = 32 2 6 = 64 2 7 = 128 2 8 = 256 2 9 = 512 2 10 =1024=1 K 2 16 = 65536

9. Negative Number Representation: Two’s Complement If the number is positive then the two’s complement is the same as the SM. If the number is negative then the two’s complement is obtained by adding 1to the magnitude bits of the one’s complement. The sign bit is unchanged. The two’s complement is widely used in computers to represent signed integers. In most languages such as Pascal and C an integer variable is represented in a 16-bit two’s complement representation.

10. Basic Logic Gates Truth Table Logic Expression Gate Symbol Logic Function

11. Basic Logic Gates with Inverted Outputs

12. Circuit Implementation of a Logic Expression with Gates

13. Truth Tables Truth table of a logic circuit is a table showing all the possible input combinations with the corresponding value of the output. Examples:

14. Logic expression and truth table of a logic circuit

15. Analyzing a logic circuit using timing diagrams Logic 0 Logic 1

16. Decoders A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of outputs ‘m’, where m= 2 n Only one of the outputs is enabled at a time. The output enabled is the one specified by the binary number formed at the inputs of the decoder. On the circuit below, the inputs of the decoder are connected on three switches, forming the number 5 [(101) 2 ], thus only LED #5 will be ON

17. 2 to 4 Line Decoder:

18. Internal structure of a 2-to-1 multiplexer. The design of a 2-to-1 multiplexer is shown below. If S=0 then the output “Y” has the same value as the input “I0” If S=1 then the output “Y” has the same value as the input “I1”

19. 4-to-1 Multiplexer (MUX) S1S0O 00I0 01I1 10I2 11I3

20. 1-bit Full Adder

21. 4-bit Full Adder (Ripple-Carry Adder) To obtain a 4-bit full adder we cascade four 1-bit full adders, by connecting the Carry Out bit of bit column M to the Carry In of the bit column M+1, as shown below. The Carry In of the Least Significant column is set to zero. Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.

22. Review questions How many input/output signals are present in a –5-to-32 decoder? –32-to-1 MUX? –32-bit Ripple-Carry Adder (RCA)? How many 2-to-1 MUXs are required to build a 32-to-1 MUX? Design a logic unit with 2 data inputs (A, B), three select inputs (S2, S1, S0) and the following specifications: S2S1S0O 000A AND B 001A OR B 010A XOR B 011A NAND B 100A NOR B 101A XNOR B 110A΄A΄ 111B΄B΄

23. The Toggle (T) Edge Triggered Flip Flop The T edge triggered flip flop can be obtained by connecting the J with the K inputs of a JK flip directly. When T is zero then both J and K are zero and the Q output does not change. When T is one then both J and K are one and the Q output will change to the opposite state, or toggle.

24. D and T Edge Triggered Flip Flops :- Example Complete the timing diagrams for : (a)Positive Edge Triggered D Flip Flop (b)Positive Edge Triggered T Flip Flop (c)Negative Edge Triggered T Flip Flop (d)Negative Edge Triggered D Flip Flop

25. Finite state machine block diagram State memory: Set of n flip-flops that hold the state of the machine (up to 2^n distinct states) Next state logic: Combinational circuit that determines the next state as a function of the current state and the input Output logic: Combinational circuit that determines the output as a function of the current state and the input

26. Finite State Machine types Mealy machine: The output depends on the current state and input Moore machine: The output depends only on the current state –State = output state machine: A Moore type FSM where the current state is the output

27. State diagram A state diagram represents the states as circles and the transitions between them as arrows annotated with inputs and outputs

28. Analysis of FSMs with D flip-flops Determine the next state and output functions Use the functions to create a state/output table that specifies every possible next state and output for any combination of current state and input

29. EXAMPLE

30. Next state equations and state table for example A+=Ax+Bx B+=A΄x Y=(A+B)x΄ ABxA+B+y 000000 001010 010001 011110 100001 101100 110001 111100

31. A+=Ax+Bx B+=A΄x Y=(A+B)x΄ ABxA+B+y 000 001 010 011 100 101 110 111

32. Sequential circuit design methodology From the description of the functionality or the state/timing diagram find the state table Encode the states if the state table contains letters Find the necessary number of flip-flops Select flip/flop type From the state table, find the excitation tables and output tables Using Karnaugh maps find the flip-flop input logic expressions Draw the circuit logic diagram

33. Often we have to implement an algorithm in hardware instead of software Algorithm is a well defined procedure consisting of a finite number of steps to the solution of a problem. It is often hard to translate the algorithm into an FSM. ASMs can serve as stand-alone sequential network model. Algorithm Implementation

34. Algorithmic State Machine Used to graphically describe the operations of an FSM more concisely Resembles conventional flowcharts – differs in interpretation. Conventional flowchart – sequential way of representing procedural steps and decision paths for algorithm -No time relations incorporated ASM chart – representation of sequence of events together with timing relations between states of sequential controller and events occurring while moving between steps

35. ASM Chart Three basic elements: state box, decision box and conditional box -State and decision boxes used in conventional flowcharts -Conditional box characteristic to ASM State box -Used to indicate states in control sequence Register operations and output signals used to control generation of next state written

36. State box Represents one state in the ASM. May have an optional state output list. Single entry. Single exit to state or decision boxes.

37. State Box State name T3 Binary code of T3 – 011 Register operation R <- 0 START – name of outputs signal generated in this stage

38. Decision box Provides for next alternatives and conditional outputs. Conditional output based on logic value of Boolean expression involving external input variables and status information. Single entry. Dual exit, denoting if Boolean expression is true or false. Exits to decision, state or conditional boxes.

39. Decision Box Input condition subject to test inside diamond shape box Two or more outputs represent exit paths dependant on value of condition in decision box Two paths for binary based conditions

40. Conditional output box Provides a listing of output variables that are to have a value logic-1, i.e., those output variables being asserted. Single entry from decision box. Single exit to decision or state box.

41. In state T1 Output signal START generated Status of input E checked If E = 1, R <- 0, otherwise remains unchanged Conditional operation executed depending on result of coming from decision box Conditional Box

42. ASM Block Consists of the interconnection of a single state box along with one or more decision and/or conditional boxes. It has one entry path which leads directly to its state box, and one or more exit paths. Each exit path must lead directly to a state, including the state box in itself. A path through an ASM block from its state box to an exit path is called a link path.

43. Timing Considerations All sequential elements in datapath and control path controlled by master-clock generator. Does not necessarily imply single clock in design. Multiple clocks can be obtained through division of clock signals from master-clock generator. Not only internal signals, but also inputs synchronized with clock. Normally, inputs supplied by other devices working with the same master clock. Some inputs can arrive asynchronously Difficult to handle by synchronous designs, require asynchronous glue-logic.

44. In conventional flowchart, evaluation of each chart element takes one clock cycle Step 1: Reg A incremented Step 2: Condition E evaluated Step 3: Based on evaluation results, state T2, T3 or T4 entered In ASM the entire block considered as one unit All operations within block occurring during single edge transition The next state evaluated during the same clock System enters next state T2, T3 or T4 during transition of next clock ASM Block

45. An ASM block describes the operation of the system during the state time in which it is in the state associated with the block. The outputs listed in the state box are asserted. The conditions indicated in the decision boxes are evaluated simultaneously to determine which link path is to be followed. If a conditional box is found in the selected path then the outputs found in its output list are asserted. Boolean expression may be written for each link path. The selected link paths are those that evaluate to logic-1.

46. Example 2 Extract the FSM diagram from the ASM diagram