1. PLL with VCO Band Selection Ko-Chi Kuo

2. Auto Band Selection Outline PART I: Concept Review n Auto Band Selection Concept n Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. ) PART II: Circuit Design Review n Divide 8 and ECL to CMOS Circuit and Simulation n 9 Bit Programmable Counter and Simulation n Band Selection Interface Schematic and Simulation n Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Simulation n Summary

3. PART I:Band Selection Concept Review PART I: Concept Review n Auto Band Selection Concept n Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

4. Auto Band Selection Concept n The need of Auto Band Selection n Multi-Band Solution Using CMOS Binary Digital Varactor n Frequency Coverage of RFVCO over 8 Bands n Requirements for Band Selection Algorithm to Work n How the Band Selection Works n Frequency Comparison Concept n Frequency Resolution with 8 Band RF VCO n Frequency Resolution with 4 Band IF VCO n Band Select Circuit Design n Band Select Circuit Timing Diagram n Summary

5. The need of Auto Band Selection VCO frequency variations over temperature(2%) and process(%9) The minimum RF VCO Frequency Coverage(at RF LO) 2.30GHz 2.xxGHz 60MHz: Minimum required coverage for WCDMA at any temperature 2.yyGHz 2.36GHz

6. n Frequency Tuning is achieved through: u CMOS Binary Band-Select Capacitors u Small Integrated PIN Diode Varactor Total Frequency Coverage at given process and temp. Frequency Vtune Multi-band Solution Using CMOS Binary Digital Varactor

7. Frequency Coverage of RF VCO over 8 Bands Band overage is 84%. The band coverage at (000) is 230 MHz for Core VCO, 115MHz after divide-by-2. * courtesy from Dawn Wang’s RFVCO CDR presentation. Desired Cover Range 4.6 –4.72 GHz (2.56%) Guard bands for process & temperature 5.4% each

8. 1.Band Selection is performed each time a new channel is selected. 2.There is minimum overlap (  f ) between two adjacent bands to cover the maximum expected temperature drift (+/-100 degree C) once a band is chosen. Frequency (LO) Vtune...... Overlap:  f 0.5 2.35 Band Switching Decision Point Given Minimum Band Overlap (  f) : 105MHz 1.100degree (C) temperature drift: +/- 40MHz 2.BS Algorithm tolerance: +/- 4MHz 3.Vtune Bias Error: +/- 5MHz 4.Band separation Mismatch: This is accounted for in the Minimum Band Overlap (  f)   f > 2 x (40M + 4M + 5M) = 98MHz Requirements for Band Selection Algorithm to Work Band=0 Band=3 Band=2 Band=1............

9. Comparison at 2.35Volts reduces algorithm error caused by Vtune voltage variations and Overlap variations. 1.At Power Up: -- All registers set to zero (as default) -- Vtune is set to 2.35V 2.Load (f LO (MHz) + 49) / 8 into Band Select Register thru Serial Interface. -- This loading action triggers Band Select Algorithm 3.Compare Frequencies. -- (f LO + 49MHz) / 8 > f VCO ? 4.Band selection counter (register) counts up as long as (f LO + 49MHz) / 8 > f VCO. 5.Freeze BS Counter when: (f LO + 49MHz) / 8 < f VCO 6.Vtune voltage control is released. * Above procedures are automatic except steps 1 and 2. How the Band Selection Works Frequency (LO) Vtune...... Overlap:  f 0.5 2.35 Band Switching Decision Point Band=0 Band=3 Band=2 Band=1............

10. ABS Interconnection Diagram & Operation R-register of IF PLL is used to generate 1MHz f_REF for both RF and IF ABS circuits. BS_Man overrides ABS algorithm and allows manual control of Band_Sel BS_Reset resets all the registers inside ABS circuit blocks. RF_ABS f REF BS_Man BS_Reset EN( BS Enable) Vtune RBS VCO_in f REF _Off Synthesizer RF_VCO Vtune BS 3bits 2.35V 9bits

11. ABS Operation Flowchart Start / Power Up As default: f REF = disabled Freeze = Low (Disabled) BS_Reset = Low BS_Man = Low Vtune = 2.35 Volts Load R-Register of IF PLL thru SI to output 1MHz Load [ f LO (MHz) + 49] / 8 to RBS & IBS thru S.I. f LO is desired VCO frequency for IF and RF PLL Loading RBS & IBS tirggers EN high – triggers BS operation Reset BS to zero f REF is enabled Cnt_Start enabled at f REF From here on operation is synchronized to f REF Start Down Count Down Counter reaches ‘0’ before next f REF ? Increase BS by one Reload DN_Counter Freeze goes High f REF = Disable Freeze BS Reset all other Reg’s to ‘0’ Vtune_Release goes High Vtune (VCO input) is reconnected to loop filter output for normal operation Ready for normal operation of PLL END Load RBS (or IBS) value onto DN_Counter yes

12. Vtune Band 2.35V freq (GHz) 8/freq (nS) 297*8/freq (  S) Band02.283.511.042 Band12.313.461.028 Band22.343.421.015 Band32.383.371.002 Band42.403.330.988 Band52.443.290.976 Band62.473.250.964 Band72.493.210.952 Frequency Resolution with 8 Band RF VCO 1.The resolution of band selection counter is set to (f LO + 49MHz) / 8 so that difference between two band can be larger enough to chose the right band. In this case, each difference is about 3~4 clock cycles.

13. Vtune Band 2.35V freq (GHz ) 8/fre q (nS) 195*8/fre q (  S) Band01.505.331.040 Band11.535.231.020 Band21.585.060.987 Band31.654.850.945 Frequency Resolution with 4 Band IF VCO 1.The resolution of band selection counter is set to (f LO + 34MHz) / 8 so that difference between two band can be larger enough to chose the right band. In this case, each difference is about 4~8 clock cycles. Given Minimum Band Overlap (  f) : 82MHz 1.100degree (C) temperature drift: +/- 26MHz 2.BS Algorithm tolerance: +/- 4MHz 3.Vtune Bias Error: +/- 4MHz 4.Band separation Mismatch: This is accounted for in the Minimum Band Overlap (  f)   f > 2 x (26M + 4M + 4M) = 68MHz

14. Freeze 8 9-bit Down Cntr 9-bits Load (f LO (MHz) + 49) / 8 every 1  sec using : RBS register Cntr = high ? VCO 2330MHz / 8 = 291MHz Vtune Band_Sel * Using Clk and En inputs of S.I. to manually control Band Selection * BSR, RBS and RMB are inputs from S.I. Freeze RMB Vtune_Release TWIF_Clk TWIF_ENB RMB BS_Man 3-bit Counter 3-bit Band_Sel BS_Cnt DQ rst f REF f VCO / 8 DQ Q Freeze Band Selection Circuit Design(RF) Freeze DN_Cnt Reload Freeze_b BS_enable DQ Q DQ Q EN BS_enable FREF RMB Freeze EN DQ Q DQ Q DN_Cnt Reload Freeze BSR rst BSR f REF CNT_Start EN SWITCH 2.35V Vtune LPF_out * Vtune is determined by vtune release LPF_out is from off-chip LPF Decode_C EN TWIF_ENB Vtune_Release DQ f VCO / 8 BSR

15. Band Selection Circuit Design(IF) Freeze 9-bit Down Cntr 8-bits Load (f LO (MHz) + 34) / 8 every 1  sec using : RBS register Cntr = high ? 1554MHz / 8 =194MHz * Using Clk and En inputs of S.I. to manually control Band Selection * BSR, RBS and IMB are inputs from S.I. Freeze IMB Vtune_Release TWIF_Clk TWIF_ENB IMB BS_Man 3-bit Counter 3-bit Band_Sel BS_Cnt Freeze Reload Freeze_b BS_enable DQ Q DQ Q EN DQ Q DQ Q DN_Cnt Reload rst BSR Decode_C SWITCH 2.35V Vtune LPF_out * Vtune is determined by vtune release LPF_out is from off-chip LPF EN TWIF_ENB 8 VCO Vtune Band_Sel f VCO / 8 Freeze DN_Cnt BS_enable Vtune_Release DQ f VCO / 8 DQ rst f REF DQ Q FREF RMB Freeze Reload Freeze BSR rst f REF CNT_Start BSR

16. Band Selection Circuit Timing Diagram f REF EN Freeze BS_Enable Cnt_Start Reload Dn_Cnt BS_Cnt

17. n Band Selection is necessary for the RF and IF VCOs in order to overcome the VCO frequency drift due to the process and temperature variations. n The proposed Band Selection Algorithm takes 2  sec per band and less than 20  sec(RF)/12  sec(IF) to accomplish Automatic Band Selection. n Frequency comparison is made through counting the frequency of f RF /8 signal during 1  sec (all digital solution.) n Small overhead in silicon area and No Extra Current Consumption. Summary of Auto Band Selection Algorithm

18. PART I:Band Selection Concept Review PART I: Concept Review n Auto Band Selection Concept n Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

19. Auto Band Selection Interface with other Blocks(PLL, VCO, LPF, S.I.) n RF Top Schematic of ABS, PLL, VCO, LPF, and S.I. n IF Top Schematic of ABS, PLL, VCO, LPF, and S.I.

20. Serial Interface TWIF_Clk Data TWIF_EN RF PLL RPE RF Low Pass Filter Iout RRC RPC RSC RCP CPS RF VCO Vtune Band_Sel RF Auto Band Selection LPF_out Oscillator TCXO vcop_rf vcon_rf RBS BSR RMB Decode_C RVE SWITCH Vtune_release 2.35V FREF (From IF PLL) RF TOP of ABS, PLL, VCO, LPF, S.I.

21. IF TOP of ABS, PLL, VCO, LPF, S.I. Serial Interface TWIF_Clk Data TWIF_EN IF PLL IPE IF Low Pass Filter Iout IRC IPC ICP CPS IF VCO Vtune Band_Sel IF Auto Band Selection LPF_out Oscillator TCXO vcop_if vcon_if IBS BSR IMB Decode_C IVE SWITCH Vtune_release 2.35V FREF (From IF PLL)

22. PART II: Circuit Design Review n Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation n 9 Bit Programmable Counter Schematic and Simulation n Band Selection Interface Schematic and Simulation n Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Top Level Simulation n ABS, PLL, VCO, LPF Top Level Simulation n Summary PART II:Band Selection Circuit Design Review

23. Auto Band Selection: Divide 8, Biasing, CML to CMOS Circuits n Auto Band Selection: Divide 8, Biasing n Corner Simulation Condition n Circuit Simulation Result n Simulation Summary

24. Auto Band Selection: Divide 8 and Biasing Auto Band Interface LPF_out Vtune_release Band Selection RBS (from S.I.) Band_Sel FREF (From IF PLL) 8 9-bit Down Cntr Control Logic Bias circuit Vbias PWD VCO_vtune (to VCO vtune) (from LPF) (to VCO Band select lines) 3-bit Counter Power on Reset circuit Control Signal (from S.I.) Reset Vtune_release

25. Auto Band Selection Divide 8 and CML to CMOS circuit Simulation Corner Process: bipolar fast(3), resistor fast(3), temp =-20  C Process: bipolar fast(3), resistor slow(-3), temp =-20  C Process: bipolar slow(-3), resistor fast(3), temp =-20  C Process: bipolar slow(-3), resistor slow(-3), temp =-20  C Process: bipolar fast(3), resistor fast(3), temp =85  C Process: bipolar fast(3), resistor slow(-3), temp =85  C Process: bipolar slow(-3), resistor fast(3), temp =85  C Process: bipolar slow(-3), resistor slow(-3), temp =85  C Frequency is set at 2.5GHz, Supply Voltage is 2.85V

26. Auto Band Selection: Divide 8 and CML to CMOS circuit Simulation Result Freq=2.5G Supply= 2.85V (1/freq/8)current Design_bfrf, -20  C 3.2n2.147mA Design_bfrs, -20  C 3.2n3.296mA Design_bsrf,-20  C 3.2n2.179mA Design_bsrs, -20  C 3.2n3.324mA Design_bfrf, 85  C 3.2n2.122mA Design_bfrs, 85  C 3.2n3.285mA Design_bsrf, 85  C 3.2n2.258mA Design_bsrs, 85  C 3.2n3.488mA

27. Auto Band Selection Divide 8 and CML to CMOS circuit Simulation Summary Minimu m Typic al Maximu m Units Power Supply2.8533.15V Current@2.85V2.1223.488mA Operating Frequency 2.362.5GHz

28. PART II: Circuit Design Review n Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation n 9 Bit Programmable Counter Schematic and Simulation n Band Selection Interface Schematic and Simulation n Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Top Level Simulation n ABS, PLL, VCO, LPF Top Level Simulation n Summary

29. Auto Band Selection: 9 Bit Programmable Counter n Auto Band Selection: 9 Bit Programmable Counter n Corner Simulation Condition n Circuit Simulation Result n Power down/up Simulation Result n Corner Simulation Result n Simulation Summary

30. Auto Band Selection: 9 Bit Programmable Counter Auto Band Interface LPF_out Vtune_release Band Selection RBS (from S.I.) Band_Sel FREF (From IF PLL) 8 9-bit Down Cntr Control Logic Bias circuit Vbias PWD VCO_vtune (to VCO vtune) (from LPF) (to VCO Band select lines) 3-bit Counter Power on Reset circuit Control Signal (from S.I.) Reset Vtune_release

31. Auto Band Selection Circuit Design 9 Bit Programmable Counter Simulation Corner Process: nfet fast(3), pfet fast(3), temp =-20  C Process: nfet fast(3), pfet slow(-3), temp =-20  C Process: nfet slow(-3), pfet fast(3), temp =-20  C Process: nfet slow(-3), pfet slow(-3), temp =-20  C Process: nfet fast(3), pfet fast(3), temp =85  C Process: nfet fast(3), pfet slow(-3), temp =85  C Process: nfet slow(-3), pfet fast(3), temp =85  C Process: nfet slow(-3), pfet slow(-3), temp =85  C Frequency is set at 2.5GHz, Supply Voltage is 2.85V

32. Auto Band Selection 9 Bits Counter Corner Simulation Results Freq=2.5G, Supply=2.85 1/(freq/8)/312)current Design_nfpf, -20  C 998.397nS1.052mA Design_nfps, -20  C 998.397nS1.227mA Design_nspf,-20  C 998.397nS1.389mA Design_nsps, -20  C 998.397nS1.593mA Design_nfpf, 85  C 998.397nS1.12mA Design_nfps, 85  C 998.397nS1.31mA Design_nspf, 85  C 998.397nS1.478mA Design_nsps, 85  C 998.397nS1.678mA

33. Auto Band Selection 9 Bits Counter Simulation Summary Minimu m TypicalMaxim um Units Power Supply2.8533.15V Current@2.85V1.0521.678mA Division2298~30 8 512Count s Operating Frequency 2.362.5GHz

34. PART II: Circuit Design Review n Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation n 9 Bit Programmable Counter Schematic and Simulation n Band Selection Interface Schematic and Simulation n Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Top Level Simulation n ABS, PLL, VCO, LPF Top Level Simulation n Summary

35. Auto Band Selection: Band Selection Interface n Auto Band Selection: Band Selection Interface n Auto Band Selection: Band Selection Interface Buffer Circuit worst case simulation n Auto Band Selection: Band Selection Interface Circuit Simulation Result n Auto Band Selection: Band Selection Interface with VCO, PLL, LPF Simulation Result n Simulation Summary

36. Auto Band Selection: Reference Clock Generator Auto Band Interface LPF_out Vtune_release Band Selection RBS (from S.I.) Band_Sel FREF (From IF PLL) 8 9-bit Down Cntr Control Logic Bias circuit Vbias PWD VCO_vtune (to VCO vtune) (from LPF) (to VCO Band select lines) 3-bit Counter Power on Reset circuit Control Signal (from S.I.) Reset Vtune_release

37. Auto Band Selection Band Selection Buffer Worst Case Simulation Simulation caseSimulation parameter :Temp, supply voltage, MOS corner model AC worst case: Smallest PM (open loop ) 85  C, 2.85V supply, PMOS=3, NMOS=-3 Transient case: largest delay 85  C, 2.85V supply, PMOS=-3, NMOS=-3

38. Auto Band Selection Interface:Buffer AC Phase Margin Simulation Phase Margin=60  AC open loop gain=70dB

39. Auto Band Selection Interface:Buffer Step Input Response Simulation Settling time=200ns vout Step input

40. Auto Band Selection Interface Simulation Result LPF_in (comes from LPF) Power_down Vtune_release PWD (generated by this interface) VCO_Vtune (goes to VCO) This is power on period ABS find the right band and shut down the ABS VCO_Vtune=2.35V (settled 300ns after power on) VCO_Vtune=LPF_in (after ABS find the right band)

41. Auto Band Selection Interface with VCO, PLL, LPF Simulation Result LPF initial condition :0.5V VCO_Vtune Vtune_release

42. Auto Band Selection Interface with VCO, PLL, LPF Simulation Result LPF initial condition :2.35V VCO_Vtune Vtune_release

43. Auto Band Selection Interface Simulation Summary n The Interface circuit provides the VCO vtune voltage based on ABS status, one is a fixed 2.35V, the other source is from off-chip LPF output. n When ABS select the right band, it generates the power down signal to shut down the current of ABS circuit. n Simulation result shows that after interface circuit shut down ABS, PLL and VCO can still handle LPF initial condition.

44. PART II: Circuit Design Review n Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation n 9 Bit Programmable Counter Schematic and Simulation n Selection Interface Schematic and Simulation n Band Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Top Level Simulation n ABS, PLL, VCO, LPF Top Level Simulation n Summary

45. Auto Band Selection: Band Power On Reset DFF Circuit n Auto Band Selection: Band Power On Reset DFF Circuit n Circuit Simulation Result

46. Auto Band Selection: Band Power On Reset DFF Circuit Auto Band Interface LPF_out Vtune_release Band Selection RBS (from S.I.) Band_Sel FREF (From IF PLL) 8 9-bit Down Cntr Control Logic Bias circuit Vbias PWD VCO_vtune (to VCO vtune) (from LPF) (to VCO Band select lines) 3-bit Counter Power on Reset circuit Control Signal (from S.I.) Reset Vtune_release

47. Auto Band Selection Reset DFF Simulation Result Power On Reset Power On

48. PART II: Circuit Design Review n Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation n 9 Bit Programmable Counter Schematic and Simulation n Selection Interface Schematic and Simulation n Band Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Top Level Simulation n ABS, PLL, VCO, LPF Top Level Simulation n Summary

49. Auto Band Selection: VCO and Switch Phase Noise Test n Circuit Simulation Result n Auto Band Selection: VCO and Switch (with divide 2) Phase Noise Test Bench n Circuit Simulation Result n Simulation Summary

50. Auto Band Selection: VCO and Switch Phase Noise Test n Circuit Simulation Result n Simulation Summary

51. Auto Band Selection :VCO Simulation Result VCO with SwitchVCO without Switch -120.252dBc/Hz@1MHz-120.04dBc/Hz@1MHz

52. Auto Band Selection VCO and Switch Simulation Summary n Auto Band Selection: VCO and Switch Phase Noise Test Bench Simulation result shows no degradation between VCO with switch and VCO without switch. n Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test Bench Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch. n Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch

53. Auto Band Selection VCO and Switch Simulation Summary n Auto Band Selection: VCO and Switch Phase Noise Test Bench Simulation result shows no degradation between VCO with switch and VCO without switch. n Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test Bench Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch. n Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch

54. Auto Band Selection VCO and Switch Simulation Summary n Auto Band Selection: VCO and Switch Phase Noise Test Bench Simulation result shows no degradation between VCO with switch and VCO without switch. n Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test Bench Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch. n Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch

55. Serial Interface TWIF_Clk Data TWIF_EN RF PLL RPE RF Low Pass Filter Iout RRC RPC RSC RCP CPS RF VCO Vtune Band_Sel RF Auto Band Selection LPF_out Oscillator TCXO vcop_rf vcon_rf RBS BSR RMB Decode_C RVE SWITCH Vtune_release 2.35V Auto Band Selection Top Level Simulation FREF (From IF PLL)

56. ABS Top Level Simulation Result BS0 BS1 BS2 CNT_Start DN_CNT BS_Cnt Vtune_Release Band 7 is selected

57. ABS Top Level Simulation Result BS0 BS1 BS2 CNT_Start DN_CNT BS_Cnt Vtune_Release Band 7 is selected

58. ABS, PLL, LPF, VCO Top Level Simulation n ABS, PLL, LPF, VCO : Top Level Simulation n Circuit Simulation Result n ABS, PLL, LPF, VCO, S.I Top Level Schematic and List of interconnection

59. ABS, PLL, LPF, VCO Top Level Simulation n ABS, PLL, LPF, VCO : Top Level Simulation n Circuit Simulation Result n ABS, PLL, LPF, VCO, S.I Top Level Schematic and List of interconnection

60. ABS, PLL, LPF, VCO Top Level VerilogA Model Simulation Result Vtune_release LPF_in CP_out PLL settle PLL start normal function

61. PART II: Circuit Design Review n Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation n 9 Bit Programmable Counter Schematic and Simulation n Reference Clock Schematic and Simulation n Selection Interface Schematic and Simulation n Band Reset DFF Schematic and Simulation n VCO Phase Noise Simulation n Auto Band Selection Top Level Simulation n ABS, PLL, VCO, LPF Top Level Simulation n Summary

62. Auto Band Selection Circuit Simulation Summary Band Selection Circuit start chose band 2  S after EN signal enabled and takes additional up to 16  S to chose the right band for VCO. The total selection time is 18  S(RF), 10  S(IF). The Power Up takes 1  S which is smaller than 2  S. Whenever channel changed, both RF and IF ABS will be enabled to select the right band again. Band Selection Circuit will shut down when the right band is selected. The simulation of VerilogA model: PLL,VCO, ABS, LPF shows that ABS can work properly with other related blocks. The phase noise of VCO has 0.15dBc/Hz @ 1MHz degradation by adding additional switch on the vtune line.