1. Tony GivargisUniversity of California, Riverside & NEC USA1 Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design Tony D. Givargis & Frank Vahid Department of Computer Science University of California Riverside, CA 92521 {givargis,vahid}@cs.ucr.edu Jörg Henkel C&C Research Laboratories, NEC USA 4 Independence Way, Princeton, NJ 08540 henkel@ccrl.nj.nec.com A DAC scholarship and a NSF grant in part supported this research.

2. Tony GivargisUniversity of California, Riverside & NEC USA2 Introduction Systems-on-a-chip (SOC) era –increased chip capacity –parametrizable core based system design Large power/performance tradeoffs possible just by varying bus/cache parameter values [givargis99] But, simulation based cache/bus power evaluation is slow

3. Tony GivargisUniversity of California, Riverside & NEC USA3 Introduction We present a two-step approach for fast cache power evaluation –collect intermediate data using simulation –use equations to rapidly predict power –couple with a fast bus estimation approach Our approach is –orders of magnitude faster than simulation –yields good accuracy

4. Tony GivargisUniversity of California, Riverside & NEC USA4 Target Architecture Bus A CPUI-Cache D-Cache Bridge Peripheral 1 Peripheral Bus Peripheral 2Peripheral n Memory Bus B

5. Tony GivargisUniversity of California, Riverside & NEC USA5 Focus on Cache/Bus Parameters Bus ABus B Peripheral 1 Peripheral Bus Bridge CPU I-Cache D-Cache Peripheral 2Peripheral n Memory Power dissipation breakdown in a Digital Camera example

6. Tony GivargisUniversity of California, Riverside & NEC USA6 Cache Parameters Bus A Peripheral 1 CPU I-Cache D-Cache Bridge Peripheral Bus Peripheral 2Peripheral n Memory Bus B

7. Tony GivargisUniversity of California, Riverside & NEC USA7 Cache Parameters TagIndexOffset VTDVTD == Mux Data Associativity Cache Size Line Size

8. Tony GivargisUniversity of California, Riverside & NEC USA8 Bus Parameters Bus A Peripheral 1 CPU I-Cache D-Cache Bridge Peripheral Bus Peripheral 2Peripheral n Memory Bus B

9. Tony GivargisUniversity of California, Riverside & NEC USA9 Bus Parameters Bus A/B Mux Demux Mux Demux Bus A/B Mux Demux Mux Demux Change Bus Width [givargis98] C1C1 C2C2 C 1 < C 2

10. Tony GivargisUniversity of California, Riverside & NEC USA10 Bus Parameters Bus A/B Encoder Decoder Encoder Decoder Change Data Representation (Bus Invert) [Stan95] Bus A/B Encoder Decoder Encoder Decoder invert_ctr Reduce Bus Switching

11. Tony GivargisUniversity of California, Riverside & NEC USA11 Bus Parameters 0100101101001011 1001011010010110 Hamming Dist = 6 0100101101001011 0 0110100101101001 1 inverted_ctr Binary Encoding Bus-Invert Encoding Hamming Dist = 3

12. Tony GivargisUniversity of California, Riverside & NEC USA12 Related Work Important to explore various cache and bus parameters for best performance and power [Wilton96][Li98][givargis99] –large number of cache/bus configurations –need to estimate power/performance in constant time Trace stripping [Wolf99], configuration ordering, single pass simulation [Kirovski])

13. Tony GivargisUniversity of California, Riverside & NEC USA13 Approach Overview Given a trace of memory refs Cache parameters Size (S) Line/block-size (L) Associativity (A) Compute # of misses (N) Size (S) # of misses (N) } } }

14. Tony GivargisUniversity of California, Riverside & NEC USA14 Approach Overview Capture improvements obtainable by: –changing line-size at small/large values of cache-size –changing associativity at small/large values of cache-size

15. Tony GivargisUniversity of California, Riverside & NEC USA15 Approach Overview Bus equation: m items/second (denotes the traffic N on the bus) n bits/item k bit wide bus binary encoding random data assuption

16. Tony GivargisUniversity of California, Riverside & NEC USA16 Approach Overview Bus equation: m items/second (denotes the traffic N on the bus) n bits/item k bit wide bus bus-invert encoding random data assumption

17. Tony GivargisUniversity of California, Riverside & NEC USA17 Experiments Bus ABus B Peripheral 1 Peripheral Bus Bridge CPU I-Cache D-Cache Peripheral 2Peripheral n Memory Cache parameters – size: 128, 256, 512, 1k, 2k, 4k, 8k, 16k, 32k – assoc: 2, 4, 8 – line: 8, 16, 32 Bus Parameters – width: 4, 8, 16, 32 – code: binary/bus-invert Analyzed 45K sets exhaust. – 3d-Image – MPEG – CKey – Diesel 5kB to 230kB of C code

18. Tony GivargisUniversity of California, Riverside & NEC USA18 Experiment Setup C Program Trace Generator Cache Simulator CPU Power ISS Performance + Power Memory Power Bus Simulator I/D Cache Power Dinero [Edler, Hill] CPU power [Tiwari96]

19. Tony GivargisUniversity of California, Riverside & NEC USA19 Experiment Results Diesel application’s performance Blue (light-gray) is obtained using full simulation Red (dark-gray) is obtained using our equations 4% error 320x faster

20. Tony GivargisUniversity of California, Riverside & NEC USA20 Experiment Results Diesel application’s energy consumption Blue (light-gray) is obtained using full simulation Red (dark-gray) is obtained using our equations 2% error 420x faster

21. Tony GivargisUniversity of California, Riverside & NEC USA21 Experiment Results CKey application’s performance Blue (light-gray) is obtained using full simulation Red (dark-gray) is obtained using our equations 8% error 125x faster

22. Tony GivargisUniversity of California, Riverside & NEC USA22 Experiment Results CKey application’s energy consumption Blue (light-gray) is obtained using full simulation Red (dark-gray) is obtained using our equations 3 % error 125x faster

23. Tony GivargisUniversity of California, Riverside & NEC USA23 Experiment Results 125 - 400x speedup 1-18% absolute error (power & performance) 2% average power error Time (hours) Power Error (%)

24. Tony GivargisUniversity of California, Riverside & NEC USA24 Conclusion Presented a technique for rapidly estimating the power and performance of cache and bus sub-systems –orders of magnitude faster than exhaustive simulation –yields good accuracy Enable exploration of parameters in parameterized system-on-a-chip architecture