1. 1 3/22/02 Benchmark Update u Carnegie Cell Library: “Free to all who Enter” s Need to build scaling model of standard cell library s Based on our open 0.35 micron library (real extracted data) s This semester: basic standard cells s This summer: memories u Timing Models s Actual timing probably is not as important as variations s Simple 1-order models of speed and variations

2. 2 3/22/02 Circuit Benchmarks u New vertical benchmarks: s All designed to comply with common network interface s Interoperability, portability for IP blocks s Why is this interesting/useful for benchmarks? t IOs and other system-level issues make it hard to compare benchmarks s Also good for education Network Tile Processing Element Network Tile Processing Element Network Tile Processing Element Network Tile Processing Element Network Tile Processing Element Network Tile Processing Element

3. 3 3/22/02 New Circuit Bencmarks u The Network Tile: for streaming applications u The Processing Elements: s Morphable Floating Point Multiplier: t FP mult and vector add, integer multiply and integer MAC and shift s Morphable Floating Point Adder: t FP add and integer add and shift s Programmable Integer ALU s Programmable FIR filter s SIMD Adder (with funky completion logic) u All about 20-100k gates each s Can be combined into systems of arbitrary size s Network limits effective Rent’s Exponent s *Actually Network connectivity would determine Rent Exponent t Currently planning 2-D network, creating Rent Exponent of 0.5

4. 4 3/22/02 Dynamic Network Tiles PE TILE PE TILE PE TILE PE: the component at this node in the network TILE: the network component

5. 5 3/22/02 Dynamic Network System PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE PE TILE Reference Clock distribution through network Each tile generates own clock Interface decoupled via FIFOs New Placement Problem: space utilization vs. distance

6. 6 3/22/02 Target Architecture: Pipelined Arrays u Limited Feedback u Long/short wires predictable u Clock Skew u Important Application Domain

7. 7 3/22/02 Classic Wire Length Models D A C B D A C B

8. 8 3/22/02 Wire Path Length u Every block is a pipeline stage u Impossible to determine every wire length from floorplan blocks u Wire Path Length (WPL) measures the distance between consecutive registers

9. 9 3/22/02 Wire Path Length D A C B D A C B

10. 10 3/22/02 Results Key u Classic s Different random starting position every time s Classic Move Set - Swap u Classic + LSP s Same legal starting position every time s Classic Move Set - Swap u New s Same legal starting position every time s New Move Set - Insert/Delete

11. 11 3/22/02 IDEA 60 Block Design

12. 12 3/22/02 1-D DCT u 12 Pipeline Stages u Synthesis Speed - 2.25 ns.  Synthesis Area - 668,323  m 2

13. 13 3/22/02 Unfloorplanned

14. 14 3/22/02 Classic

15. 15 3/22/02 Classic + LSP

16. 16 3/22/02 New

17. 17 3/22/02 Results