1. PSU CS 106 Computing Fundamentals II Introduction HM 1/3/2009

2. 2 © Dr. Herbert G. Mayer Agenda Computers, Programming & You Simple Terms Generic Computer Flynn Classification 1966 Architecture Attributes Uniprocessor Architectures Multiprocessor Architectures Hybrid Architectures Instruction Set Architecture (ISA)

3. 3 © Dr. Herbert G. Mayer Computers, Programming & You Ideally, Computer is black box –reading input –knowing What To Do with its input –generating corresponding output Black box must be programmed (flexible function), or could be hard-wired (fixed function) Programmed to understand What To Execute in Detail To read your input, when, how far, and interpreted how To generate output in a way we can understand Thus, black box becomes increasingly white box Working differently across different manufacturers’ products –Ever got an Apple ® drawing to display on a MS application? So hire programmers! Problem solved Except we cannot understand one another, hence this class!

4. 4 © Dr. Herbert G. Mayer Simple Terms SW - discuss HW - discuss FW - discuss Algorithm Programming, Program Systems Programming Personal Computer Desktop, Pedestal Computer Laptop – THE future of practical computing Minicomputer Supercomputer

5. 5 © Dr. Herbert G. Mayer Generic Computer Single Chip Microprocessor AKA CPU Stack Code & Data free OS region Heap Space Chip-Set AKA IO and Memory Controller ALU pc r0 r1 r2 r(n-1) Register File FPU Ctrl Unit L2 Cache L1 Cache Main memory

6. 6 © Dr. Herbert G. Mayer Flynn Classification 1966 Single-Instruction, Single-Data Stream (SISD) Architecture –(e.g. PDP-11) Single-Instruction, Multiple-Data Stream (SIMD) Architecture –(Array Processors, e.g. Solomon, Illiac IV, BSP, TMC) Multiple-Instruction, Single-Data Stream (MISD) Architecture –(possibly pipelined architecture, VLIW, EPIC) Multiple-Instruction, Multiple-Data Stream Architecture –(true multiprocessor yet to be built)

7. 7 © Dr. Herbert G. Mayer Architecture Attributes Main memory (AKA main store), local, external, shared, distributed Program instructions stored in main memory Stored in main memory: data, stack, heap, OS space, free space, IO space Which memory unit is addressable: bit, byte, word? Generally byte Instruction pointer (instruction counter, program counter), other special regs Von Neumann memory bottle-neck, data to/from memory travel on bus Accumulator –or registers– holds result of arithmetic-logical op Memory Controller handles memory accesses from processor to memory IO Controller handles memory access of peripherals Both jointly constitute Chipset (memory controller & IO controller) Processor units: FP units, Integer unit, Control unit, register file, pathways UP or MP Integer arithmetic, logical arithmetic Floating-point arithmetic: numeric precision, internal precision in machine registers vs. external data precision (data format) Instruction-level parallelism

8. 8 © Dr. Herbert G. Mayer Uniprocessor Architectures Single Accumulator Architecture –earliest systems late 1940s General-Purpose Register Architectures (GPR) –E.g. personal computer 2-Address Architecture (GPR with one operand implied) –e.g. IBM 360 3-address Architecture (GPR with all instruction operands explicit) –e.g. VAX 11/70 Stack Machines –e.g. B5000, B6000, HP3000 Vector Architecture

9. 9 © Dr. Herbert G. Mayer Multiprocessor Architectures Shared Memory Architecture MP Distributed Memory Architecture MP Systolic Architecture Data Flow Machine Contemporary multi-core CPUs

10. 10 © Dr. Herbert G. Mayer Hybrid Architectures Superscalar Architecture VLIW Architecture Pipelined Architecture EPIC Architecture

11. 11 © Dr. Herbert G. Mayer Instruction Set Architecture (ISA) ISA is boundary between Software (SW) and Hardware (HW) –Specifies logical machine visible to programmer & Compiler –Is functional specification for processor designers Specified by an ISA: –Operations: what operation to perform now & which operation to perform next –Temporary Operand Storage in the CPU: accumulator, stacks, registers –Number of operands per instruction –Operand location: where and how to specify the operands –Type and size of operands –Instruction-to-Binary Encoding

12. 12 © Dr. Herbert G. Mayer Instruction Set Architecture (ISA) ISA: Dynamic – Static Interface (DSI)