1. Integrated Silicon Photonics – An Overview Aniruddha N. Udipi

2. What’s wrong with electrical signaling? Power and delay fundamentally increase with length –Repeaters can help with delay, but further increase power – cannot afford this Signal integrity issues –Limits on the number of “drops” (DIMMs, say) –Long, fast, wide – pick any two Very slow growth of pin count and per pin bandwidth –Chip-edge and socket-edge bandwidth severely limited –Increasing pressure due to increasing communication requirements with multi-thread, multi-core, multi-socket We need a disruptive new technology 2

3. 3 Say Hello to Silicon Photonics Simply put, replace wires and electrons with waveguides and photons Advantages –Lower energy consumption, distance independent –Higher bandwidth, Dense Wavelength Division Multiplexing (DWDM) –Better scalability, no pin limits –In some cases, you simply cannot use electrical connections to satisfy the projected requirements Where? –Started with large distances (Atlantic ocean large) –Increased viability over smaller distances as technology improves and matures –Next, interconnect inside datacenters - between racks –Eventually, intra-rack, intra-board, intra-chip…

4. Photonic Interconnect Basics 4 Laser Modulator Channel Detector 010100011101010100011101 101110001010101110001010 Design Space – Laser, modulation, channel, detection

5. Photonic Components

6. On-chip Laser Vertical Cavity Surface Emitting Laser (VCSEL) –One of the largest volume (and hence, cheapest) lasers currently in use –Is often integrated on-chip –Enables “direct modulation” You directly turn the laser on or off in accordance with the data being transmitted –Not fully CMOS compatible –Also, does not support DWDM 6

7. Off-chip Laser Distinct component, actual construction not important A single laser source can feed multiple channels –You just have a power splitter with the laser –Potential to be cost-effective in systems with multiple transmission channels (multiple memory channels, say) Needs “external modulation” –Laser is on continuously, but you either block the light or not, depending on the data being transmitted Supports DWDM Under active consideration 7

8. Modulator 8 “OFF” STATE“ON” STATE input output Waveguide Courtesy: D. Fattal and R. Beausoleil, HP Labs

9. Modulator Operation How do you go between “ON” and “OFF”? –Charge injection (HP Labs) –Charge depletion (Sun) These rings can be made “wavelength selective” with proper sizing during fabrication There are also “disc” modulators; similar operational principle, only the physical implementation is different 9 Courtesy: Xu et al. Optical Express 16(6), 4309–4315 (2008)

10. Channel Silicon waveguide –Used on-chip –Moderate loss, crossover issues Hollow metal waveguide –Used for slightly longer distances, at the board level –Low loss, ease of fabrication Free space –Just use air! –Bunch of micro-mirrors and micro-lenses guide the light around –On-chip use Fiber optic cable –Off-chip interconnect 10

11. Miscellaneous Components Power splitters – Y splitter – divides the total power among several channels –1:2, 1:4, and 1:8 splitters available –Other than drop in strength, signal is unaffected Detectors – Seem to be simple photodetectors, I haven’t seen much variation or focus on this component Power guides –Mux/Demux Couplers 11 Courtesy: Beamer et al. ISCA 2010

12. Features / Design Considerations

13. Dense Wavelength Division Multiplexing One of the primary advantages of photonics: excellent bandwidth density Each wavelength of light transmits one bit, supported by a bunch of “wavelength selective” ring resonators –Each wavelength can operate independently Total number of supported wavelengths limited by increasing coupling losses between rings as spacing is tightened Up to 67 wavelengths theoretically possible Each wavelength can run at ~10Gbps, giving a total of 80 GB/s of bandwidth per channel 13

14. Laser Power Considerations The detectors need to receive some minimum amount of photonic power in order to reliably determine 0/1 –Depends on their “sensitivity” Going from source to destination, there are several points of power loss – the waveguide, the rings, splitters, couplers, etc. Work backwards to determine total input laser power required Also some concerns about “non-linearity”, when total path loss exceeds a certain amount –Rule of thumb ~20dB 14

15. Static Power Considerations Modulating rings are sized at fabrication time to be tuned to a particular wavelength However, this tends to drift during operation Not only will this hurt this specific wavelength, but may also drift into adjacent wavelengths in DWDM systems, causing interference This drift can be controlled by heating, called “trimming” These heaters consume non-trivial amounts of power Large static power, cannot under-utilize or leave idle 15

16. Applications

17. My personal research focus Application to the processor-memory interface –Ideal candidate in many respects Scalability, bandwidth, energy The questions we’re trying to answer: –how can we best apply photonics to the memory subsystem? –Should we replace all interconnects with photonics? –what would the role of electrical signaling be? –how invasive would the required memory (DRAM) modifications be? Off-chip laser, external ring-based modulation, off-chip fiber and on-chip silicon waveguides 17

18. Interconnects in the Memory system 18 DRAM Array – I/O On-chip Interconnect DRAM I/O – Processor Off-chip Interconnect

19. Photonics vs. electronics Photonics –Lower dynamic energy –Higher static energy –Cannot be over-provisioned or left idle –Perfect for the shared off-chip interconnect, helps break the pin barrier Electronics –Higher dynamic energy –Lower static energy –Can be over-provisioned or left idle 19

20. How deep should photonics go on die? 20 Electrical Energy Photonic Energy

21. Single-die system (Prior work) 21 Argues for specialized memory dies with photonics deep inside – in this case, one stop for each quarter of the chip

22. But.. Realistic systems cannot have a single die per channel You simply need more capacity –3D stacking –Daisy-chaining of these 3D stacks Many more rings The effect of photonics’ static energy much more pronounced Argues for reducing photonic use How? 22

23. Proposed design 23

24. Proposed Design Introduce a 3D Stacked “Interface Die” This die contains all photonic components All further traversal is electrical –TSVs to move between dies vertically –Efficient low-swing wires on-die Helps break the pin-barrier Uses photonics on the heavily used shared off-chip interconnect, amortizes static energy Uses electrical signaling locally, where activity is low 24

25. An analogy 25 Can you really run the METRO to every house?

26. Realistic System 26 Use a single stop per stack, on the interface die

27. Advantages of the proposed system Energy consumption –Fewer photonic resources, without loss in performance –Rings, couplers, trimming Industry considerations –Does not affect design of commodity memory dies –Same memory die can be used with both photonic and electrical systems –Same interface die can be used with different kinds of memory dies – DRAM, PCM, STT-RAM, Memristors 27

28. Final System Compared to the best fully- optical extension of the state- of-the-art photonic DRAM design –23% reduced energy consumption –4X capacity per channel –Potential for performance improvements due to increased bank count –Non-disruptive to commodity memory design 28

29. High-radix Datacenter Routers (HP Labs) 29

30. Simplify! Need high dimension network to reduce hop count Bandwidth per port has to scale over time Photonics are perfect.. –Switch size unconstrained by device IO limits –Port bandwidth scalable by increasing number of wavelengths –Optical link ports can directly connect to anywhere within the data centre –Greatly increased connector density, reduced cable bulk –64-128 DWDM port router possible 30

31. Macro-chips (Sun Labs, Oracle) Die sizes are limited by process yield For a given compute power requirement, therefore, you need several smaller chips Large bandwidth requirement between these chips With photonics, such a macro-chip design can approach a large chip performance 31

32. On-chip Interconnect (Rochester) 32

33. Ok, but when will all of this see light of day? Adoption will be gradual, over smaller distances –km scale – it’s already happened – Under-sea cables –100m scale – in progress –m scale – just starting –cm scale – in the lab but relatively ready –mm scale – also in the lab but not ready for prime time Technology exists, constantly being improved by smart people in labs all over the world Maturity, manufacturing infrastructure and cost are the big barriers –Catch 22! First products expected in ~1year (Intel Light Peak) – USB replacement –Optical backplane for server racks ~2 years –Fancier applications will likely take ~5-8 years 33