1. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (1) Garcia, Fall 2006 © UCB Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 26 – CPU Design: Designing a Single-cycle CPU, pt 2 2006-10-30 Halloween plans?  Try the Castro, SF! halloweeninthecastro.com Tomorrow 2005-10-31, runs until 11pm …go at least once… Happy Halloween, everyone!

2. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (2) Garcia, Fall 2006 © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

3. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (3) Garcia, Fall 2006 © UCB Step 3: Assemble DataPath meeting requirements Register Transfer Requirements  Datapath Assembly Instruction Fetch Read Operands and Execute Operation

4. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (4) Garcia, Fall 2006 © UCB 3a: Overview of the Instruction Fetch Unit Common to all instructions: Fetch the Instruction: mem[PC] Update the program counter:  Sequential Code: PC  PC + 4  Branch and Jump: PC  “something else” 32 Instruction Word Address Instruction Memory PC clk Next Address Logic

5. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (5) Garcia, Fall 2006 © UCB 3b: Add & Subtract R[rd]  R[rs] op R[rt] Ex.: addU rd,rs,rt Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields ALUctr and RegWr: control logic after decoding the instruction oprsrtrdshamtfunct 061116212631 6 bits 5 bits Already defined the register file & ALU 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

6. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (6) Garcia, Fall 2006 © UCB Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay “Critical path” (longest path through logic) determines length of clock period Clk........................

7. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (7) Garcia, Fall 2006 © UCB Register-Register Timing: One complete cycle Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

8. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (8) Garcia, Fall 2006 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate 016212631 6 bits16 bits5 bits immediate 0161531 16 bits 0 0 0 0 0 0 0 0 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

9. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (9) Garcia, Fall 2006 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate 016212631 6 bits16 bits5 bits immediate 0161531 16 bits 0 0 0 0 0 0 0 0 Already defined 32-bit MUX; Zero Ext? What about Rt register read?? 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc 01 0 1 ALU 5 RegDst

10. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (10) Garcia, Fall 2006 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc 01 0 1 ALU 5 RegDst

11. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (11) Garcia, Fall 2006 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5 ?

12. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (12) Garcia, Fall 2006 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5

13. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (13) Garcia, Fall 2006 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5

14. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (14) Garcia, Fall 2006 © UCB 3f: The Branch Instruction beq rs, rt, imm16 mem[PC] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction’s address  PC = PC + 4 + ( SignExt(imm16) x 4 ) else  PC = PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

15. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (15) Garcia, Fall 2006 © UCB Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits Already have mux, adder, need special sign extender for PC, need equal compare (sub?) imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 = Equal

16. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (16) Garcia, Fall 2006 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr Equal Instruction Imm16RdRtRs clk PC 00 4 nPC_sel PC Ext Adr Inst Memory Adder Mux 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5

17. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (17) Garcia, Fall 2006 © UCB An Abstract View of the Implementation Data Out clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions clk ALU

18. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (18) Garcia, Fall 2006 © UCB Peer Instruction A. Our ALU is a synchronous device B. We should use the main ALU to compute PC=PC+4 C. The ALU is inactive for memory reads or writes. ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

19. CS61C L26 CPU Design : Designing a Single-Cycle CPU II (19) Garcia, Fall 2006 © UCB °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Next time! Summary: Single cycle datapath Control Datapath Memory Processor Input Output