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5.8 Exclusive-OR Gates and Parity Circuits ReturnNext Exclusive-OR(XOR) Gates Exclusive-NOR(XNOR) Gates x ⊕ y=x · y+x · y x ⊙ y=x · y+x · y 0 1 1 0 0 1.

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Presentation on theme: "5.8 Exclusive-OR Gates and Parity Circuits ReturnNext Exclusive-OR(XOR) Gates Exclusive-NOR(XNOR) Gates x ⊕ y=x · y+x · y x ⊙ y=x · y+x · y 0 1 1 0 0 1."— Presentation transcript:

1 5.8 Exclusive-OR Gates and Parity Circuits ReturnNext Exclusive-OR(XOR) Gates Exclusive-NOR(XNOR) Gates x ⊕ y=x · y+x · y x ⊙ y=x · y+x · y 0 1 1 0 0 1 0 0 1 1 0 1 X Y Inputs x⊕yx⊕y x⊙yx⊙y Outputs

2  Equivalent symbols for XOR and XNOR gates NextBackReturn 5.8 Exclusive-OR Gates and Parity Circuits (a) XOR gates (b) XNOR gates Prove the upper symbols for XOR and XNOR is equivalent.

3  Parity Circuits (p413 Figure 5-74) NextBackReturn 5.8 Exclusive-OR Gates and Parity Circuits  The 74x280 9-Bit Parity Generator (p414 Figure 5-75) A B C D EVEN E F ODD G H I 74X280 5 12 8 9 10 11 13 1 2 4 6

4 BackReturn 5.8 Exclusive-OR Gates and Parity Circuits  Parity-Checking Applications (p415 Figure 5-76)  Parity Circuits are also used with error- correcting codes (p416 Figure 5-77)

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