1. Susmit Biswas A Pageable Defect Tolerant Nanoscale Memory System Susmit Biswas, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner susmit@cs.ucsb.edu

2. Susmit Biswas Problem Statement In a nanoscale memory system with high manufacturing defect rate, we aim to find a scheme with low static and dynamic overhead to identify and avoid the use of defective blocks and make usable memory in the granularity of 4-KByte size pages.

3. Susmit Biswas Is it a significant problem? Manufacturing defect –10 – 30% using Self-assembly DNA computing –Low yield Yield decreases with block size

4. Susmit Biswas Is it a significant problem?

5. Susmit Biswas Critical Factors Static Overhead –Bad block information Dynamic Overhead –Reading and writing latency

6. Susmit Biswas ECC Overhead source: Likharev07

7. Susmit Biswas Contribution Analytical model Defect tolerance technique –ECC, defect map, sparing Study on area benefit Fixed size block or variable size?

8. Susmit Biswas Prior Work Error Correcting Codes [Jeffery04] [Ou04] Reconfiguration using Defect Map [Tahoori05][Wang06][DeHon05][Likharev-JETC07] Built-in-self-Repair (BISR) [Bhavsar-ITC99][Schöber-ITC01][Nicolaidis-JET05] Combination of schemes [Sun06] [Likharev-JETC07][Biswas-ICCAD07]

9. Susmit Biswas Technique Benefit from all –Error Correcting Code (BCH) Strength of code –Defect Map Level of map –Spare Block Amount of sparing

10. Susmit Biswas Technique Store the defect map in unreliable memory Defect Map Reconfiguration Map

11. Susmit Biswas Technique Majority voting to provide correctness 101 111101 Majority Voter 101 Defect Map

12. Susmit Biswas Defect Map System Architecture Spare Map Metadata Data

13. Susmit Biswas Pros and Cons Pros –Locality of data and metadata –Low static overhead –High yield –Can be pipelined –Support for virtual memory system Cons –2s + 1 memory block read Locality reduces overhead

14. Susmit Biswas Results: Storage Efficiency

15. Susmit Biswas Results: Static Overhead

16. Susmit Biswas Fixed vs. Variable Block

17. Susmit Biswas Summary Defect tolerance technique –Combination of static and dynamic scheme Encoding defect-map with data –Locality of data –Low static overhead –High yield Higher yield using variable sized page –Static overhead increases

18. Susmit Biswas Future Work Efficient BCH module design Interconnect reliability by redundancy Cache design using unreliable memory

19. Susmit Biswas Contact: Susmit Biswas Arch Lab, Department of Computer Science University of California at Santa Barbara susmit@cs.ucsb.edu Online version available at: http://cs.ucsb.edu/~susmit/papers/nanoarch07_nanomemory.pdf http://cs.ucsb.edu/~susmit/papers/nanoarch07_nanomemory.pdf

20. Susmit Biswas References [Sun06] F. Sun and T. Zhang. “Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories”. Nanoarch 2006 [Wang06] G. Wang, W. Gong, and R. Kastner. “Defect- Tolerant Nanocomputing Using Bloom Filters”. ICCAD 2006 [DeHon05] A. DeHon and K. K. Likharev. “Hybrid CMOS /Nanoelectronic Digital Circuits: Devices, Architectures, and Design Automation”. ICCAD '05 [Tahoori05] M. B. Tahoori. “A Mapping Algorithm for Defect-Tolerance of Recongurable Nano-Architectures”. ICCAD ’05

21. Susmit Biswas References [Likharev07] D. Strukov and K. Likharev, “Defect-Tolerant Architectures for Nanoelectric Crossbar Memories”. Journal of Nanoscience and Nanotechnology, January 2007 [Jeffery04] C. M. Jeffery, A. Basagalar, and R. J. O. Figueiredo, “Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures”. 4th IEEE Conference on Nanotechnology 2004. [Ou04] E. Ou and W. Yang, “Fast Error-Correcting Circuits for Fault-Tolerant Memory”, MTDT, pages 8 - 12, 2004.

22. Susmit Biswas Reference [Ramón05] Ramón Compaňó, “Trends in nanoelectronics”, Journal of Nanotechnology 12, 2001 [Biswas-ICCAD07] Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner, “ Combining Static and Dynamic Defect-Tolerance Techniques for Nanoscale Memory Systems”, to appear in ICCAD 07

23. Susmit Biswas Results Metric –Storage efficiency (# physical bits/#logical bits) –Configuration data overhead