School of Electrical, Electronics and Computer Engineering University of Newcastle-upon-Tyne Baseband Digital Modulation Baseband Digital Modulation Prof.
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School of Electrical, Electronics and Computer Engineering University of Newcastle-upon-Tyne Baseband Digital Modulation Baseband Digital Modulation Prof. Rolando Carrasco Lecture Notes University of Newcastle-upon-Tyne 2007
Bit-rate, Baud-rate and Bandwidth denotes the duration of the 1 bit Hence Bit rate = bits per second All the forms of the base band signalling shown transfer data at the same bit rate. denotes the duration of the shortest signalling element. Baud rate is defined as the reciprocal of the duration of the shortest signalling element. Baud Rate = baud In general Baud Rate ≠ Bit Rate For NRZ : Baud Rate = Bit Rate RZ : Baud Rate = 2 x Bit Rate Bi-Phase: Baud Rate = 2 x Bit Rate AMI: Baud Rate = Bit Rate
Non Return to Zero (NRZ) The highest frequency occurs when the data is 1010101010……. i.e. This sequence produces a square wave with periodic time Fourier series for a square wave, If we pass this signal through a LPF then the maximum bandwidth would be 1/T Hz, i.e. to just allow the fundamental (1st harmonic) to pass.
Non Return to Zero (NRZ) (Cont’d) The data sequence 1010…… could then be completely recovered Hence the minimum channel bandwidth
Return to Zero (RZ) Considering RZ signals, the max frequency occurs when continuous 1’s are transmitted. This produces a square wave with periodic time If the sequence was continuous 0’s, the signal would be –V continuously, hence.
Bi-Phase Maximum frequency occurs when continuous 1’s or 0’s transmitted. This is similar to RZ with Baud Rate = = 2 x Bit rate The minimum frequency occurs when the sequence is 10101010……. e.g. In this case = Baud Rate = Bit rate
Digital Modulation and Noise The performance of Digital Data Systems is dependent on the bit error rate, BER, i.e. probability of a bit being in error. Digital Modulation There are four basic ways of sending digital data The BER (P) depends on several factors the modulation type, ASK FSK or PSK the demodulation method the noise in the system the signal to noise ratio Prob. of Error or BER,
Digital Modulation and Noise Amplitude Shift Keying ASK
Digital Modulation and Noise Frequency Shift Keying FSK
Digital Modulation and Noise Phase Shift Keying PSK
System Block diagram for Analysis DEMODULATOR – DETECTOR – DECISION For ASK and PSK
Using the change of variable Probability density function of noise (*)
This becomes The incomplete integral cannot be evaluated analytically but can be recast as a complimentary error function, erfc(x), defined by Equations (*) and (**) become (**)
It is clear from the symmetry of this problem that P e0 is identical to P e1 and the probability of error P e, irrespective of whether a ‘one’ or ‘zero’ was transmitted, can be rewritten in terms of v = v 1 – v 0 for unipolar signalling (0 and v ) for polar signalling (symbol represented by voltage
FM/ FSK Demodulation One form of FM/FSK demodulator is shown below In general V IN (t) will be Where is the input frequency (rad/sec)
FM/ FSK Demodulation (Cont’d) i.e Thus there are two components Component (1) is at frequency 2 f IN Hz and component (2) is effectively a ‘DC’ voltage if is constant. The cut-off frequency for the LPF is designed so that component (1) is removed and component (2) is passed to the output.
FM/ FSK Demodulation (Cont’d) The V/F characteristics and inputs are shown below Analogue FM Modulation Index
FM/ FSK Demodulation (Cont’d) The spectrum of the analogue FM signal depends on and is given by
Digital FSK Normalized frequency Deviation ratio The spectrum of FSK depends on h
FM/ FSK Demodulation (Cont’d) Consider again the output from the demodulator The delay is set to where and is the nominal carrier frequency Hence
FM/ FSK Demodulation (Cont’d) The curve shows the demodulator F/V characteristics which in this case is non linear.
Practical realization of F/V process The comparator is LIMITER – which is a zero crossing detector to give a ‘digital’ input to the first gate. This is form of ‘delay and multiply’ circuit where the delay is set by C and R with = CR