1. M -RAM (Magnetoresistive – Random Access Memory) Kraków, 7 XII 2004r

2. M-RAM M. Bernacki, S. Wąsek Information flux. Information Outside word Input Output Information transmission Information Processing Information storage DRAM, MRAM Magnetic (HDD) Optical (CD, DVD)

3. M-RAM M. Bernacki, S. Wąsek Memory categories. WHY DO WEE NEED M-RAMMEMORY ????

4. M-RAM M. Bernacki, S. Wąsek Basic attractions of M-RAM. Nonvolatility; Speed; Low-power consumption; Scalability.

5. M-RAM M. Bernacki, S. Wąsek Basic attractions of M-RAM. Transfer data to microprocessor without creating a bottleneck!

6. M-RAM M. Bernacki, S. Wąsek History and development...  M-RAM – quick view.  Magnetoresistivity.  AMR effect - 80-th.  GMR effect - 80-th.  TMR effect – 1995 year. M-RAM based on:

7. M-RAM M. Bernacki, S. Wąsek Storage and states of a bit. Storage state:  DRAM: charge of capacitor.  Flash, EEPROM: charge on floating gate.  FeRAM: charge of a ferroelectric capacitor. TMR [%] Field [Oe] MRAM: charge and spin. „1” „0” Soft ferromagnet Insulator Hard ferromagnet

8. M-RAM M. Bernacki, S. Wąsek Implementation of 1-MTJ / 1-transistor cell. Word line NiFe (free layer) CoFe (fixed layer) Ru CoFe (pinned layer) Al 2 O 3 (tunneling barrier) SAF

9. M-RAM M. Bernacki, S. Wąsek Write. Word line With digit line current Without digit line current

10. M-RAM M. Bernacki, S. Wąsek Write. Word line RA [kOhm-um 2 ] Easy axis field [Oe]

11. M-RAM M. Bernacki, S. Wąsek Read. Word line

12. M-RAM M. Bernacki, S. Wąsek Sizes of MTJ. Ferromagnet I Tunnel barrier Ferromagnet II NiFe (free layer) CoFe (fixed layer) Ru CoFe (pinned layer) Al 2 O 3 (tunneling barrier) 4nm 1..2nm 3nm

13. M-RAM M. Bernacki, S. Wąsek Other MRAM cell architectures. Twin cell arrays:  Circuit is faster than the 1T1TMR implementation.  Less atractive on a cell density and cost basis. Diode cell:  SOI diodes allow the integration of a memory with most circuits without sacrificing silicon wafer surface area.  SOI diodes suitable for this aplication haven’t been developed yet. Transistorless array:  Large reduce in cell area.  Complex circuity required to read bit state, slow read.

14. M-RAM M. Bernacki, S. Wąsek MRAM 32Kb memory segment. Bit line 31 Digit line Word line Bit line 0 Word line

15. M-RAM M. Bernacki, S. Wąsek Reference generator. R MAX R MIN Bit line Digit line Word line R REF = 1/2(R MAX + R MIN )

16. M-RAM M. Bernacki, S. Wąsek 1Mb MRAM architecture. Available modes: Active mode Sleep mode Standby mode

17. M-RAM M. Bernacki, S. Wąsek Examples and performance of M-RAM technology. Freescale semiconductors –2003/2004.  Technology: 0.18mikrons, 5-level metal CMOS, copper interconnects;  Capacity: 4MB;  Access time: 15-20ns  Technology: 0.6um, 5-level metal CMOS, copper interconnects;  Capacity: 1MB  Access time: 35ns Motorola semiconductors –2002.

18. M-RAM M. Bernacki, S. Wąsek Roadmap to future storage technologies. RRAM with CMR

19. M-RAM M. Bernacki, S. Wąsek Bio – MRAM, vision for tomorrow? MRAM array Biomolecule labeled by magnetic markers

20. M-RAM M. Bernacki, S. Wąsek References.  Wykład z przedmiotu „Magnetyczne nośniki pamięci”, AGH;  Materiały z Uniwersytetu Bielefeld: wykład „Thin films and nanostructures”;  Materiały seminaryjne z „Motorola Labs”;  Materiały z sympozjum „VLSI symposium 2002”;  www.freescale.com www.freescale.com  www.motorola.com www.motorola.com

21. M-RAM M. Bernacki, S. Wąsek Dziękujemy za uwagę