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DUAL Functional Synthesis and Verification of Finite State Machines Alan Mishchenko, PSU Anatoly Chebotarev, GIC Marek Perkowski, PSU.

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Presentation on theme: "DUAL Functional Synthesis and Verification of Finite State Machines Alan Mishchenko, PSU Anatoly Chebotarev, GIC Marek Perkowski, PSU."— Presentation transcript:

1 DUAL Functional Synthesis and Verification of Finite State Machines Alan Mishchenko, PSU Anatoly Chebotarev, GIC Marek Perkowski, PSU

2 Algorithms FSM specification using time constraints Internal data representation using BDDs Minimum-state FSM synthesis by construction Determinization and specification completion Verification using R-resolution (new method) FSM decomposition (forthcoming)

3 Practical Applications Provably correct design of real-time (reactive, hybrid) systems Protocol design and verification Synthesis of minimum state (non)deterministic FSMs FSM design for future technologies (“canonical machines”)

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5 SYNTHA Logic Synthesis and Verification of Finite State Machines Alan Mishchenko, PSU Andrey Mishchenko, Glushkov Institute, Kiev, Ukraine

6 Table method for FSM specification Transparent logic synthesis algorithms Economic implementation of next-state logic Two-level boolean optimization (Espresso) VHDL output Synthesis for testability (forthcoming) Technology mapping (forthcoming) Algorithms

7 Human-guided FSM specification and design of efficient controller Logic Synthesis of economical FSMs Building FSMs from universal blocks such as counters, shifters, EXOR modifiers Using various encodings and flip-flop types Adaptations for PLA, FPGA, ASIC Producing VHDL output Practical Applications

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9 TRACE Glimpses into the Inner Structure of “Cyclic” Boolean Functions and Autonomous FSMs Alan Mishchenko, PSU Andrey Mishchenko, Glushkov Institute, Kiev, Ukraine

10 New concept of “cyclic” boolean functions Finding “traces” of “cyclic” boolean functions for different types of flip-flops Properties of known and random functions Multi-zoom visualization using MFC Algorithms

11 Research in boolean functions Synthesis of economical control units using embedded autonomous FSMs Design of FSMs using AND/EXOR circuits optimized for speed, area, and testability Case Study: Efficient reversible counters Practical Applications

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13 MVGUD Decomposition of Multi-Valued Multi-Output Functions and Relations Marek Perkowski, PSU Stan Grygiel, PSU

14 Decomposition strategy selection Variable partitioning (new algorithms) New Data Structure for weakly-specified functions and relations (LR-partitions) Column multiplicity (graph coloring) Decomposition evaluation using DFC Iterative processing of decompositions Verification of final results Algorithms

15 Boolean and Multi-Valued Logic Synthesis Finite State Machine Decomposition Data Mining and Machine Learning Digital Image Processing Artificial Intelligence Evolutionary Algorithms Practical Applications

16 .type mv.i 9.o 1.ilb i0 i1 i2 i3 i4 i5 i6 i7 i8.ob o0.imv 2 2 2 2 2 2 2 2 2.omv 2.p 156 0 0 0 1 1 - 1 - - 1 0 1 1 0 0 - 1 - - 1 1 0 1 0 0 - 1 - - 1 0 1 0 0 - 1 1 - - 1 1 0 0 0 - 1 1 - - 1 Relation Function Relation 0 1 0 0 - 1 1 - - 1 1 0 0 0 - 1 1 - - 1 0 0 - 0 1 1 1 - - 1 0 1 - 0 1 0 1 - - 1 1 1 0 - 0 1 0 - - 1 1 0 1 - 1 0 0 - - 1 0 1 - 1 1 0 0 - - 1 0 1 0 1 - 0 - 1 - 1 - 0 1 1 0 0 - 1 - 1 0 0 - - 0 1 1 1 - 1 - - 0 0 1 0 1 1 - 1 0 1 - - 0 0 1 1 - 1.end..type mv.i 3.o 1.ilb i3 i4 i5.ob s2.1.imv 2 2 2.omv 4.p 8 0 1 1 1 0 0 1 1 1 2 1 0 0 1 1 0.end.type mv.i 3.o 1.ilb i0 i1 i2.ob s2.0.imv 2 2 2.omv 4.p 8 0 1 0 1 1 0 1 1 0 0 1 1 1 2 1 0 0 1 1 0.end..type mv.i 3.o 1.ilb i3 i4 i5.ob s2.1.imv 2 2 2.omv 4.p 8 0 1 1 1 0 0 1 1 1 2 1 0 0 1 1 0.end


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