1. 1 Efficient Multithreading Implementation of H.264 Encoder on Intel Hyper- Threading Architectures Steven Ge, Xinmin Tian, and Yen-Kuang Chen IEEE Pacific-Rim Conference on Multimedia 2003

2. 2 Outline Introduction Introduction Background Knowledge Background Knowledge Main Purpose Main Purpose Multithreaded Implementation Multithreaded Implementation Performance Results and Analysis Performance Results and Analysis Conclusions Conclusions

3. 3 Introduction Background Knowledge (1/6) H.264 H.264 High quality with low bit-rate High quality with low bit-rate Hybrid block-based MC and transform coding model. Hybrid block-based MC and transform coding model. Intensive workload of computation. Intensive workload of computation.

4. 4 Introduction Background Knowledge (2/6) SIMD technology [1] SIMD technology [1] Single Instruction Multiple Data Single Instruction Multiple Data Data level parallelism Data level parallelism Instruction Pool Data Pool PU

5. 5 Introduction Background Knowledge (3/6) SIMD example (Interpolation) SIMD example (Interpolation) a0a1a2 a3a4 a5a6a7b0b1b2 b3b4 b5b6b7 a0xb0+a1xb1a4xb4+a5xb5 a2xb2+a3xb3a6xb6+a7xb7 128bits

6. 6 Introduction Background Knowledge (4/6) Multiprocessor & Hyper Threading Multiprocessor & Hyper Threading Simultaneous Multithreading (SMT) Simultaneous Multithreading (SMT) Sharing the physical execution resources and duplicating architectural state Sharing the physical execution resources and duplicating architectural state Logical Processor Sharing execution resources

7. 7 Introduction Background Knowledge (5/6) Multiprocessor & Hyper Threading Multiprocessor & Hyper Threading Arch State Processor Execution Resource Arch State Processor Execution Resource Arch State Processor Execution Resource Arch State Traditional Dual-CPU System Hyper-Threading technology-capable Dual-CPU System

8. 8 Introduction Background Knowledge (6/6) OpenMP programming model OpenMP programming model High level application programming interface High level application programming interface Supports shared memory multi-processing Supports shared memory multi-processing

9. 9 Introduction Main Purpose (1/1) In order to speed up H.264 encoder performance In order to speed up H.264 encoder performance Parallelizing encoder by OpenMP programming model Parallelizing encoder by OpenMP programming model Multi-level (frame & slice level) data partition scheme Multi-level (frame & slice level) data partition scheme The experiments show the speedups on Intel Xeon TM system The experiments show the speedups on Intel Xeon TM system

10. 10 Implementation Overview (1/1) Dividing the H.264 encode process into multiple threads via data domain decomposition. Dividing the H.264 encode process into multiple threads via data domain decomposition. GOP, frame, slice, MB GOP, frame, slice, MB Judgements of thread granularity and proposed implementation. Judgements of thread granularity and proposed implementation.

11. 11 Implementation Thread Granularity (1/5) Slice-Level Parallelism Slice-Level Parallelism Independent Independent Breaking the dependency of MBs Breaking the dependency of MBs  Bit rate ↑  Bit rate ↑

12. 12 Implementation Thread Granularity (2/5) Slice-Level Parallelism Slice-Level Parallelism

13. 13 Implementation Thread Granularity (3/5) Frame-Level Parallelism Frame-Level Parallelism IBBP structure IBBP structure 0 (I) 3 (P) 2 (B) 6 (P)9 (P) 1 (B)4 (B)5 (B)7 (B)8 (B) 12 (P)

14. 14 Implementation Thread Granularity (4/5) Frame-Level Parallelism Frame-Level Parallelism Encode I, P-frames first Encode I, P-frames first No bit rate increasing problem No bit rate increasing problem Dependence among frames will limit the threads scalability Dependence among frames will limit the threads scalability

15. 15 Implementation Thread Granularity (5/5) Combine above two approaches Combine above two approaches Explore the parallelism among frames Explore the parallelism among slices Reach the upper limit of the thread number

16. 16 Implementation Multithreaded Implementation (1/4) Input preprocessing Input preprocessing Read uncompressed images Read uncompressed images Issue the images to encoding threads Issue the images to encoding threads Encoding Encoding Use two slice buffers to distinguish the priority of I, P and B frames Use two slice buffers to distinguish the priority of I, P and B frames Post-processing Post-processing Check the encoding status Check the encoding status Commit the result to the bit-stream Commit the result to the bit-stream

17. 17 Implementation Multithreaded Implementation (2/4) Thread 0 Thread 1 Thread 2 Thread 3 Thread 4 Input File Output File Image buffer Slice Queue 0 (I/P) Slice Queue 1 (B)

18. 18 Implementation Multithreaded Implementation (3/5) Pseudo code Pseudo code # pragma omp parallel sections { # pragma omp section { while ( there is frame to encode ) { if (there is free entry in img buffer) issue new frame to img buffer else if (there are frame encoded in img buffer) commit the encoded frame, release entry else wait; }

19. 19 Implementation Multithreaded Implementation (4/5) Pseudo code Pseudo code # pragma omp section { # pragma omp parallel num_thread (# of encoding thread) { while (1) { if ( there is slice in slice queue 0 ) encode one slice // higher priority for I/P-frames else if ( there is slice in slice queue 1) encode one slice // lower priority for B-frames else if ( all frames are encoded ) exit; else wait; }

20. 20 Performance Results Environment (1/5) Dell 530 MT workstation Dell 530 MT workstation Dual Intel Xeon processor running at 2.0GHz with HT enabled Dual Intel Xeon processor running at 2.0GHz with HT enabled 512K L2 Cache, 1G memory 512K L2 Cache, 1G memory IBM 360 Server IBM 360 Server Quad Intel Xeon processor running at 1.5GHz with HT enabled Quad Intel Xeon processor running at 1.5GHz with HT enabled 256K L2 Cache, 512K L3 Cache, 2G memory 256K L2 Cache, 512K L3 Cache, 2G memory

21. 21 Performance Results Encoder profile (1/5) All intersearch types are enabled All intersearch types are enabled Only the nearest previous frame is used for inter motion search Only the nearest previous frame is used for inter motion search Maximum search range is 16 Maximum search range is 16 1/4-pel motion vector resolution is used 1/4-pel motion vector resolution is used Quant parameter is set to 16 for all frames Quant parameter is set to 16 for all frames

22. 22 Performance Results SIMD Technology (1/5) Speedups of the key modules in H.264 encoder Speedups of the key modules in H.264 encoder

23. 23 Performance Results Speedup & Compression Efficiency Speedup and bit-rate vs. number of slice in a frame Speedup and bit-rate vs. number of slice in a frame

24. 24 Performance Results Performance with HT Technology Encoder speedsup on different sequence after multithreading Encoder speedsup on different sequence after multithreading

25. 25 Performance Results Performance with HT Technology With HT enabled, we can have 1.2x speedup. With HT enabled, we can have 1.2x speedup.

26. 26 Conclusions This paper presents efficient multithreaded implementation of H.264 encoder. This paper presents efficient multithreaded implementation of H.264 encoder. The first one who considers compression efficiency degradation as well as parallel speed up. The first one who considers compression efficiency degradation as well as parallel speed up. Speedsup ranging from 4.31 x to 4.69x on 4-CPU system with HT. Speedsup ranging from 4.31 x to 4.69x on 4-CPU system with HT. Their work demonstrates that HT can gain ~20% performance. Their work demonstrates that HT can gain ~20% performance.

27. 27 Reference [1] X. Zhou, E. Q. Li, and Y.-K. Chen, “Implementation of H.264 Decoder on General-Purpose Processors with Media Instructions,” in Proc. of SPIE Conf. on Image and Video Communications and Processing, Jan. 2003. [2] Y.-K. Chen, M. Holliman, E. Debes, S. Zheltov, A. Knyazev, S. Bratanov, R. Belenov, and I. Santos, “Media Applications on Hyper-Threading Technology,“ Intel Technology Journal, pp. 47-57, Feb. 2002. [3] D. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, I. A. Miller, and M. Upton, “Hyper-Threading Technology Microarchitecture and Architecture,’’ Intel Technology Journul, Vol. 6, QI, 2002.