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1 Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults R. Sethuram rms@qualcomm.com M. L. Bushnell bushnell@caip.rutgers.edu V. D. Agrawal vagrawal@eng.auburn.edu
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2 Outline Purpose Introduction Terms and definitions Implication Graph The New Functional Fault graph (FFG) Identify Equivalence/Dominance/Independence and redundant faults using FFG Results and analysis Conclusion
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3 Purpose Fault collapsing Reducing ATPG Time Test data volume Identifying independent faults Compaction Extension for other fault models Polynomial-time complexity
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4 Definitions Fault dominance f1 dominates f2 if every test of f2 detects f1 Fault equivalence If f1 and f2 dominate each other Fault independence If every test of f1 does not detect f2
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5 Implication Graph (IG) example Graph represents Boolean expressions Nodes represent literals, edges represent implications 1 2 3 1 2 3 1 2 3
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6 Operations on IG Transitive Closure: adds an edge For every path For every common ancestor Graph condensation 4 2 3 1 5 b d e a f g c C1C1 C2C2 C3C3 C4C4 Condense Strongly Connected Component (SCC)
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7 Functional Fault Graphs (FFG) New fault node to represent the fault detectability status a b c a sa0 a a OaOa a0a0 Complete FFG of a 2-input AND gate
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8 Deriving Information Perform transitive closure and graph condensation. Then, identify: Equivalence: Fault nodes f 1, f 2, …, f k are in one SCC Dominance: Independence: Untestable faults: f1f1 f2f2 f1f1 f2f2 f1f1 f1f1
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9 IGs are incomplete Observability relationship between stem and its branches cannot be represented It can be partially overcome If p and q are two signals such that q is the dominator of p then O p O q pq
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10 An example – i 0 dominates d 1 a b c d e f g h i k j m 1. d 1 O d O g O m and d 1 O d b 2. d 1 a j and d 1 a I 3. O m j O k and O k b O i. Hence, d 1 O i 4. d 1 i and d 1 O i. Hence, d 1 i 0
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11 Extending for other Fault Models Adding special nodes and edges in IG enables extending them for other fault models Time frame edges for implication across time frames Edges annotated with multiple bits l SR OlOl lOlOl l +1 01 l SR = Slow to raise fault
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12 Results – Fault Collapsing c6288 has several stems and our technique could not identify additional observability related implications. # Dominant Faults
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13 Results – Comparison using the circuit c1355 # Dominant Faults
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14 Results - Independent fault pairs for c432
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15 Results – Untestable delay faults * Only the first K levels of the netlist were analyzed # Transition Delay Faults
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16 Conclusion Proposed and implemented a functional fault graph for equivalence/dominance fault collapsing and identifying independent fault pairs Requires only polynomial-time algorithms Can be easily enhanced for other fault models Reduces fault set size by up to 66%
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