1. Computer Architecture Project
LDPC Belief Propagation Decoding with Multi-Threading and Hardware Acceleration
Computer Architecture Project

2. Low-Density Parity-Check Codes
Member of the error correcting codes family
LDPC codes provide performance that approaches the Shannon Limit
Block and Convolutional Codes.
Belief Propagation Algorithm for decoding
The technique that wins in all three objectives is the goal of the computer architect

3. Belief Propagation Algorithm
LLR0
LLR1
LLRn-1
Variable Nodes
Check Nodes
Log Likelihood Ratio (LLR): A measure of how confident the decoder is of the received bit being one or zero.
One such technique is…..
Research has predicted that Branch Prediction will have increasing importance as pipelines deepen and issue widths increase
The LLR messages will propagate between the nodes during each decoder iteration.
The LLR values of the Variable Nodes will converge towards the correct values.

4. Critical Computational Path
Approximated as

5. One Algorithm Implementation

6. Experiment
Locate the costly-loop and study the speedup on a multithreaded processor
Experiment Hardware Accelerator Architecture

7. XInC Microprocessor
multithreaded
16 bit
RISC
8 threads
realtime

8. Experiment Tools and Metrics
Used supplied C-compiler to generate equivalent LDPC-decoder assembly code
Instruction count as metric

9. Results Architecture Inst. Count Speedup 9611 Base case ST & HA 6958
Single Thread
9611
Base case
ST & HA
6958
1.381
Multi-Thread
1384
6.944
MT & HA
1005
9.563