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Scheduling Proposals Scheduling Group Giulio Galante, Wensheng Hua, Sundar Iyer, Isaac Keslassy, Pablo Molinero, Gireesh Shrimali, Rui Zhang
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Round-Robin Non-Round-Robin Two-Stage Switch (I) Two-Stage Switch (II) Longer Packets
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Input-Queued Packet Switch Crossbar Scheduler inputs outputs 1 N 1N.......... i,j N,N 1,1
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Round-Robin Scheduling
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Round-Robin: main properties Simple to implement 100% throughput with uniform traffic Bad throughput with non-uniform traffic
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Non-Round-Robin Scheduling Up to 100% throughput Too complex with a 100 Tbps router Computation complexity: Cell time = 64 B /160 Gbps = 3.2 ns = one clock cycle (today, 50 ns ; MWM: N 3 ) Ports: 625 (today, 32) Communication complexity Number of bidirectional links: 625 (today, 170) Information flow rate: 0.3 Gcells/s x 20 b/cell = 6 Gbps (today, 2.5Gbps)
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Round-Robin Non-Round-Robin Simple | No 100% throughput 100% throughput | Complex Two-Stage Switch (I) Two-Stage Switch (II) Longer Packets
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Two-Stage Switch (I) 1 N 1 N 1 N External Outputs Internal Inputs External Inputs First Round-RobinSecond Round-Robin [C.S.Chang et al.: http://www.ee.nthu.edu.tw/~cschang/PartI.pdf]
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Two-Stage Switch (I): main properties Simple to implement 100% throughput Possibility of using two sides of same mirrors Mis-sequencing!
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Two-Stage Switch (II) [Paper under review: http://klamath.stanford.edu/~keslassy/tmp/two-stage.pdf] NewN 3 instead of N 2
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Two-Stage Switch (II): main properties No missequencing 100% throughput Low average delay (within a bound from “optimal” output- queued switch) Idea not thoroughly studied: difficult implementation?
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Round-Robin Non-Round-Robin Simple | No 100% throughput 100% throughput | Complex Two-Stage Switch (I) 100% throughput, simple | Missequencing Two-Stage Switch (II) 100% throughput, no missequencing | Implementation? Longer Packets
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Longer packets [Tassiulas et al.: http://www.glue.umd.edu/~koushik/hoti00-kkar.ps.gz] Variable-size packets
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Round-Robin Non-Round-Robin Simple | No 100% throughput 100% throughput | Complex Two-Stage Switch (I) 100% throughput, simple | Missequencing Two-Stage Switch (II) 100% throughput, no missequencing | Implementation? Longer Packets 100% throughput, more time between computations | Implementation?
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1. Crossbar
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2. Multistage Networks Banyan Network (2x2)2 Layers of kxk switches
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