1. Firmware implementation of Integer Array Sorter Characterization presentation Dec, 2010 Elad Barzilay Uri Natanzon Supervisor: Moshe Porian

2. The need for Histograms Many image processing algorithms relay on the use of histograms. For example - Photo “auto fix” – histogram equalization Photo Min Photo Max 0 Full Dynamic Range

3. For example:

4. Project Goals Building a generic integer array sort Building a generic integer array sort firmware on an FPGA board firmware on an FPGA board Develop a comprehensive testing Develop a comprehensive testing and debugging environment. and debugging environment.

5. Project Overview  System capabilities & requirements – Sorting an array of finite integers set. – Zero latency system. – Fully debug-able. – System operation via PC interface.  Design principles – Generic implementation. – Top down design. – Error detection and handling.  System implementation on the DE2 evaluation card.  PC GUI implementation on MATLAB.  Complete development process: Characterization-> debugging platform.

6. High-level overview

7. Specifications Data input rate: one word per clk.  System outputs: sorted array, min, max, median, average, common item.  Output starts one clock after last input word.  In and out buffered UART communication with rate 115,200 bps.  PLL modulated clock 50M->60M.  Synchronized reset.

8. SORT_TOP – Inputs & Outputs Time Diagram

9. “DUDE” – Debugging Under Development Environment MATLAB based GUI for data injection, result validation and status query

10. “DUDE” – usage modes Send user defined arrays of data to be sorted. Send user defined arrays of data to be sorted. Send random arrays of data to be sorted. Send random arrays of data to be sorted. Query and show the value of registers of the system. Query and show the value of registers of the system. Verify the correctness of the sorted returned data array. Verify the correctness of the sorted returned data array. Configure system state registers. Configure system state registers. Create fully user generated packets to generate errors. Create fully user generated packets to generate errors. View bit representation of the messages sent and received. View bit representation of the messages sent and received. Logging of out/in-bound messages. Logging of out/in-bound messages.

11. Message Pack Structure SOF ID Data Length Data (Payload) CRC EOF 8 bits 1 Byte. Some constant predefined flag 1 Byte. For message tracking 2 Bytes. Specifies the length of the data segment in bytes. 1 Byte. The CRC type will be defined later. 1 Byte. Some constant predefined flag address 1 Byte. Specifies the addressed block address 1 Byte. Type options are : set, query, sort [Data Length] X Bytes. (up to 65535 bytes) Holds the data and control signal to be fed into SORT_TOP

12. Project mile stones: Mid–way presentation final presentation