1. Machine SUIF Michael D. Smith Harvard University Division of Engineering and Applied Sciences June 2000 © Copyright by Michael D. Smith 2000 All rights reserved.

2. 2 Background Goal: supply a compiler infrastructure for machine-specific optimizations profile-driven optimizations architectural investigations History: previous version supported research in computer architecture feedback-directed optimization branch prediction code layout and branch alignment global instruction scheduling program instrumentation register allocation systems for run-time optimization

3. 3 Infrastructure Criteria Should be easy to use and extend Should meet the needs of a range of users Should support multiple, disparate targets Should accommodate a variety of substrates

4. 4 Customers Those interested in building new optimizations done without detailed knowledge of target machine underlying substrate implementation written as a “parameterized” pass adding support for a new target architecture or augmenting an existing architecture developing a new IR implementation but uninterested in rewriting the optimizations

5. 5 Typical Backend Flow lower optimize realize optimize finalize layout output Object, assembly, or C code SUIF intermediate form Parameter bindings from dynamically-linked target libraries Machine-SUIF IR for real machine Machine-SUIF IR for idealized machine (suifvm)

6. 6 Infrastructure Overview Analysis libraries and optimization passes Target libraries IR definition and mapping library Substrate system yfc mlib alpha lib suif machsuif mlib suifvm lib libcfg deco mlib x86 lib opi parameterization libutil libbvd dcecse layout

7. 7 Code Example // Spill source operand i of instruction at h in n, // inserting a register-load just before h. void spill_src(InstrHandle h, int i, CfgNode* n) { Instr* mi = *h; Opnd opnd = get_src(mi, i); TypeId t = get_type(opnd); // replace operand by virtual register Opnd vr = opnd_reg(t); set_src(mi, i, vr); // load spilled value before original instruction Instr* ld = new_instr_alm(vr, load_opcode(t), opnd); insert_before(n, h, ld); } Key: IR types in red. OPI functions in blue and green.

8. 8 parameterization libcfglibutil libbvd dcecse layout alpha lib x86 lib alpha lib libcfglibutil libbvd dcecse layout parameterization x86 lib alpha lib libcfglibutil libbvd dcecse layout parameterization x86 lib yfc mlib suif machsuif mlib suifvm lib deco mlib opi Target Parameterization Analysis/optimization passes written without direct encoding of target details Target details encapsulated in OPI functions and data structures Machine-SUIF passes work without modification on disparate targets

9. 9 Supporting Architectural Experiments Example: add prefetch instruction to existing architecture goal: small architectural change  small code change Steps: add an interface library defines new OPI functions, e.g. bool is_prefetch(Instr*) can now code optimizations requiring new functions add one or more implementation libraries implement new OPI functions for particular target extend existing OPI functions for new instr, e.g. bool reads_memory(Instr*) can now run optimizations for that target x86_pf lib x86 lib +

10. 10 Interface Library (prefetch) #ifndef PREFETCH_PREFETCH_H #define PREFETCH_PREFETCH_H #include class PrefetchContext { public: virtual ~PrefetchContext() { } virtual bool is_prefetch(Instr*); }; bool is_prefetch(Instr*); extern "C" void init_prefetch(SuifEnv*); #endif /* PREFETCH_PREFETCH_H */ #include "prefetch.h" bool PrefetchContext::is_prefetch(Instr *instr) { return dynamic_cast (the_context) ->is_prefetch(instr); } extern "C" void init_prefetch(SuifEnv* suif_env) { init_machine(suif_env); }

11. 11 Implementation Library (x86pf) #include "x86pf.h" bool PrefetchContextX86Pf::is_prefetch(Instr* mi) { return (get_opcode(mi) == xo_prefetch); } bool MachineContextX86Pf::reads_memory(Instr* mi) { if (is_prefetch(mi)) return true; return MachineContextX86::reads_memory(mi); } class CodeGenX86Pf : public CodeGenX86 { protected: virtual void translate_any(Instr* mi, InstrList* l) { OneNote n = take_note(mi, k_instr_opcode); if (n.get_value() == "prefetch") { /* generate instruction */ } else CodeGenX86::translate_any(mi, l); }; CodeGen* SuifVmContextX86Pf::target_code_gen() const { if (cached_code_gen) return cached_code_gen; cached_code_gen = new CodeGenX86Pf; return cached_code_gen; } class PrinterX86Pf : public PrinterX86 { protected: virtual void print_instr_alm(Instr* mi) { if (is_prefetch(mi)) { /* print it */ } else PrinterX86::print_instr_alm(mi); } }; Printer* MachineContextX86Pf::target_printer() const { if (cached_printer) return cached_printer; cached_printer = new PrinterX86Pf; return cached_printer; } Context* context_creator_x86pf() { return new X86PfContext; } extern "C" void init_x86pf(SuifEnv* suif_env) { init_x86(suif_env); init_prefetch(suif_env); k_x86pf = "x86pf"; the_context_creator_registry[k_x86pf] = context_creator_x86pf; } #ifndef X86PF_X86PF_H #define X86PF_X86PF_H #include const int xo_prefetch = LAST_X86_OPCODE + 1; #undef LAST_X86_OPCODE #define LAST_X86_OPCODE xo_prefetch class PrefetchContextX86Pf : public PrefetchContext { public: bool is_prefetch(Instr*); }; class MachineContextX86Pf : public MachineContextX86 { public: bool reads_memory(Instr*); Printer* target_printer() const; }; class SuifVmContextX86Pf : public SuifVmContextX86{ public: CodeGen* target_code_gen() const; }; class X86PfContext : public virtual Context, public virtual MachineContextX86Pf, public virtual PrefetchContextX86Pf, public virtual SuifVmContextX86Pf { }; extern "C" void init_x86pf(SuifEnv*); extern IdString k_x86pf; #endif /* X86PF_X86PF_H */

12. 12 suif machsuif mlib opi parameterization alpha lib suifvm lib x86 lib libcfglibutil libbvd yfc mlib deco mlib dcecse layout Substrate Independence Optimizations, analyses, and target libraries are substrate-independent Machine SUIF is built on top of SUIF You could replace SUIF with Your Favorite Compiler Deco project at Harvard uses this approach

13. 13 Contents of Current Release Interface libraries machine (basic IR types, code finalization, assembly language and C printing), code generation control flow graph, control flow analysis, bit vector dataflow instrumentation (block, branch, load/store) Target libraries Compaq Alpha, Intel x86, suifvm Optimization passes common subexpression elim., dead code elim., peephole graph-coloring register allocation Converters s2m, il2cfg, cfg2il, m2a, m2c Documentation (in noweb) overview, user’s guide, extender’s guide, cookbook implementation documents for each interface library

14. 14 Contents of Next Release Interface libraries static single assignment (SSA) register allocation instruction scheduling Optimization passes copy propagation loop-invariant code motion procedure inlining superblock and basic block scheduling Other debugging support using stabs

15. 15 Supporting Cast Students and technical staff Glenn Holloway, Erven Rohou Deborah Abel, Ramy Adeeb, Gang Chen, Allyn Dimock, Kathleen Durant, Eric Feigin, Nick Gloy, Juraj Hlavac, Adon Hwang, Russ Ross, Stuart Schechter, Jason Simmons, Vijak Sethaput, Omri Traub, Dario Vlah, Dave Walker, Cliff Young, Conan Yuan Research homepage http://www.eecs.harvard.edu/machsuif Supporting institutions DARPA, NSF AMD, Compaq/Digital, HP, IBM, Intel, Microsoft