1. FF-1 9/30/2003 UTD Practical Priority Contention Resolution for Slotted Optical Burst Switching Networks Farid Farahmand The University of Texas at Dallas

2. FF-2 9/30/2003 UTD Overview t OBS Overview t Major issues in OBS t Switch node architecture of the OBS t Hardware prototyping of the scheduler unit t Hardware simulation results

3. FF-3 9/30/2003 UTD Optical Burst Switching (OBS) t Assemble IP packets into data bursts l Transmit bursts following their headers by an offset l Separated in space and time l Headers are processed electronically l Data bursts are passed through the optical switches

4. FF-4 9/30/2003 UTD OBS Switching Issues t Burst scheduling scheme l Channel selection and reservation for the arriving data burst F First-Fit F Latest Available Unscheduled (with and without Void Filling) t Contention resolution technique l Resolution of contention between data bursts F Buffering F Deflection routing F Wavelength conversion F Burst dropping

5. FF-5 9/30/2003 UTD OBS Switching Issues t Burst transmission schemes l Slotted: Bursts are transmitted on slot boundaries l Unslotted: Bursts can be transmitted at any time

6. FF-6 9/30/2003 UTD Switch Node Architecture DEMUX/MUX and Phase Alignment Switch Fabric BHP PROCESSOR SCHEDULER

7. FF-7 9/30/2003 UTD Hardware Implementation of the Control Packet Processor t Fast processing time l Must be fast l Minimize software t Scalable with a generic design l Can be used for any burst reservation scheme t Low cost l Implementable in an off-the-shelf programmable component (FPGA) Our main emphases: Practical approach to designing the Control Packet Processor

8. FF-8 9/30/2003 UTD Control Packet Processor Architecture t Architectures l Centralized l Distributed t Centralized architecture l Similar to input queuing l Single scheduler

9. FF-9 9/30/2003 UTD Control Packet Processor Architecture t Distributed architecture l Similar to virtual output queuing l Parallel scheduling F One per destination t Advantages l Minimizing head-of-queue blocking l Higher reliability l Allowing concurrent scheduling t Disadvantage l High memory requirement F Each Destination Queue must be sized for the worst case

10. FF-10 9/30/2003 UTD Scheduling Mechanisms in the Scheduler Block t Scheduling mechanism l Latest Available Unscheduled t Contention resolution technique l Latest Drop Policy (LDP) F With offset-time-based QoS l Shortest Drop Policy (SDP) F Supports unlimited service differentiation F Performs better than the Latest Drop Policy

11. FF-11 9/30/2003 UTD Comparing SDP and LDP Performance t Single switch with 4 edge nodes t Each port has 4 channels t Full utilization of wavelength converters t Max data burst duration is 20 slots / Exponentially distributed t 3 levels of service differentiation t Performance metric: Burst Loss Rate (BLR)

12. FF-12 9/30/2003 UTD Hardware Prototyping of the Control Packet Processor t Basic assumptions l Slotted transmission of BHPs l Shortest Drop Policy (SDP) l Parallel scheduling t Receiver Block l All BHP are verified for correct parity and framing l Each request is reformatted, time stamped, and passed on to the proper Destination queue t Destination Queues t Scheduler

13. FF-13 9/30/2003 UTD Hardware Prototyping of the Scheduler t Arbiter t Scheduler Core Section l Processor l Channel Manager l Update Switch Setup t Statistics Accumulator

14. FF-14 9/30/2003 UTD Hardware Prototyping of the Scheduler P inputs along with the counter signal Flow Control; QoS control Checks Start and End times; Reserve Requests One per channel If reservation was successful regenerate BHP

15. FF-15 9/30/2003 UTD Illustration of the Scheduler Operation t Three Channels t Assuming all Channel Queues are empty initially Time HoQ CQ0CQ1CQ2 B1 Time = i B2 Time = i+1 B3 B4B5 Time = i+6 Time = i+7

16. FF-16 9/30/2003 UTD Scheduler Prototype t Implemented on Altera EP20k400E FPGA l 2.5 million gates l Maximum clock rate of 840 MHZ t Core section modeled by Celoxica DK design suite l Initially modeled using C-language l Modified into Handel-C language l Compiled and translated into a gate level VHDL code t Other blocks were designed using VHDL code t Tested, verified, and synthesized l Cadance (NcSim) l Quartus II

17. FF-17 9/30/2003 UTD Hardware Simulation Results Number of clock cycles required to processes packets in the Destination Queue

18. FF-18 9/30/2003 UTD Hardware Simulation Results Number of NAND gates requires to design the scheduler unit

19. FF-19 9/30/2003 UTD So in Conclusion…… t A key issue in implementing the OBS is designing a fast and efficient BHP processor t We presented alternative architectures for the BHP packet processor t We discussed several scheduling algorithms and their performance t We presented hardware results in terms of the cost and scalability

20. FF-20 9/30/2003 UTD So in Conclusion…… Interested? Looking for something to do? or just Curious?

21. FF-21 9/30/2003 UTD End of Slides!

22. FF-22 9/30/2003 UTD Practical Priority Contention Resolution for Slotted Optical Burst Switching Networks Farid Farahmand, Vinod M. Vokkarane, Jason P. Jue The University of Texas at Dallas

23. FF-23 9/30/2003 UTD Control Packet Processor Architecture t Architectures l Centralized l Distributed t Centralized architecture l Similar to input queuing l All BHP are verified for correct parity and framing l Single scheduler l Each request is time stamped QoS (1 bits) Dest (2 bits) Ing DCG (2 bits) Ing DC (4 bits) Length (4 bits) Offset (5 bits) Parity (8 bits) Header (8 bits) QoS (1 bits) Ing DCG (2 bits) Ing DC (4 bits) Length (4 bits) Offset (5 bits) T (8 bits) RX BLOCK

24. FF-24 9/30/2003 UTD OBS Switching Issues t Burst transmission schemes l Slotted: Bursts are transmitted on slot boundaries l Unslotted: Bursts can be transmitted at any time F Simpler to implement F ?????Higher loss (due to unpredictable burst characterization)

25. FF-25 9/30/2003 UTD So in Conclusion…… t A key issue in implementing the OBS is designing a fast and efficient BHP processor t We presented alternative architectures for the BHP packet processor t We discussed several scheduling algorithms and their performance t We presented hardware results in terms of the cost and scalability