1. ECE x26 Laboratory 4 Pavan Gunda

2. Overview Lab4 is the culmination of all your efforts of both the ECE x25 and ECE x26 labs. Integrates the designs built in Lab 2 and Lab3 Design consists of a little over 1000 transistors (from 2 transistors in inverter)

3. Experiment Integrate the Designs of Lab 2 and Lab 3

4. Experiment The generated layout of Lab 4 is going to be completely different from that of Lab2 and Lab3 +

5. Experiment

6. Results No need to submit the propagation delay tables Estimated delays are expected for parallel load Show the Verilog simulation for the standard test flow Verification programs for –Maximum Shift Clock for normal operation –Maximum Shift Clock for Scan

7. Results Effective capacitive loads –On the input of L1 latch = 26.5 fF –On the output of L2 latch = 25.3 fF

8. Results