1. Die-Hard SRAM Design Using Per-Column Timing Tracking
Shi-Yu Huang and Ya-Chun Lai
Feb. 10, Las Vegas (IC-DFN)
Design Technology Center (DTC)
National Tsing-Hua University, HsinChu, Taiwan

2. Timing Tracking Scheme
Outline
Introduction
Timing Tracking Scheme
Traditional Replica-Based Scheme
Our Scheme
Experimental Results
Conclusion

3. Nanometer Effects on SRAMs
Worse Device Mismatch
Larger Leakage Current
Could trigger
a yield crisis!
Wider Variations of R and C
Lower VDD (smaller noise margins)
Worse Supply & Coupling Noise
Uncertain Delay

4. SRAM Memory ArchitectureCS
bit line WE OE A9
word line A8
Row
Decoder . A0
Sense Amplifier / Drivers
A19
Column Decoder
A10
Input-Output
(M bits)

5. Reading An SRAM Cell An SRAM Cell 1 cell current pulsed wordlineQ’ Q 1
cell
current
An SRAM Cell BL BL BL
Bitlines’ Waveforms

6. Two Types of Sense Amplifiers
A Sense Amplifier
Continuous Type
Latch Type
Sense
Enable

7. Three Major Problems for SRAM
Mismatch in Bit Cells and Sense Amplifiers
Vt mismatch shrinks the noise margin
Bitline Leakage Current
Could cause failure for READ operations
Timing Tracking
When to turn on sense amplifiers?
When to turn off wordline? (pulsed wordline)

8. X-Calibration for Leakage Tolerance (Presented in Last IC-DFN)
Leakage is calibrated in two steps:
Transform the effects
of the bitline leakage
to a Voffset between (BL, BL)
Leakage
Current 1 1
cell
cell
cell
cell
cell
cell BL
cell BL
Deduct Voffset
from the input of the sense amplifier
When performing sense amplification
cell
1.8V
1.5V
X-calibration circuit
S.A.

9. Die Photo of Test Chip X-Calibration BIST 1.373mm Conventional 1.108mm
SRAM Type
Conventional
Our
X-Calibration
Array Organization
1Kb cells
(32 rows × 32 columns)
Technology
TSMC 0.18um CMOS 1P6M
Area
486um × 265um
(100%)
486um × 285um
(107.6%)
Access Time
(1.8V)
1.89 ns
1.93 ns
(102%)
Supply Current
(mA)
3.7 mA
4.15 mA
(112%)
1.108mm
1.373mm
BIST
Conventional
X-Calibration

10. Shmoo Plots Target speed: 150MHz @ 250C
Measurement result: Leakage tolerance improved by 317%
Pass
Fail
Ileak=76.6uA
Supply Voltage (V)
Conventional
Pass
Ours with
X-Calibration
Supply Voltage (V)
Fail
Ileak=320uA
Injected Leakage Current (uA)

11. Timing Tracking Scheme
Outline
Introduction
Timing Tracking Scheme
Traditional Replica-Based Scheme
Per-Column Timing Tracking Scheme
Experimental Results
Conclusion

12. Traditional Scheme – Replica Bitline
Property: replica bitline pair develops a logic signal (i.e., sense enable)
when an accessed bitline pair builds up 100mV signal
replica bitline pair
decoder
active wordline
accessed
logic
sense amps
CLK
Ref: B. S. Amrutur et al., “A replica technique for wordline and sense control in low-power SRAMs,”
IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp , Aug

13. Problems of Replica Bitline Based Timing Control
The factors on the speed of a bitline pair: leakage, RC, driving of cell
 Each column could have its own bitline development speed
 A single sense enable control is susceptible to sensing errors
Read cycle
Read cycle
Voltage (V)
BL / BL SE

14. Adaptive Sensing Control
Each sense amp. adapts to its current driving bitline pair!
Voltage (V)
Read cycle
BL / BL SE

15. Operating Flow Typical READ control steps Added timing tracking steps
Row address decoding
Timing tracker start-up
Wordline activation
Timing tracker monitoring
Bitline discharging
ΔVBL>100mV?
S.E. active ? N Y N Y
Sense enable generation
Sense amplification
Timing tracker disabling

16. Controller, Input Buffer, Address Buffer
Overall Architecture
Row
Decoder WL
Driver BL BL MC MC MC MC WL
Cell Array
MUX2
MUX2
det_en
Timing
Tracker
Timing
Tracker se SA SA
Controller, Input Buffer, Address Buffer
Latch&
Buffer
Latch&
Buffer
I/O Circuitry

17. Transient Waveforms for Read
Row
Decoder WL
Driver BL BL
CLK MC MC
BL / BL
MUX2 WL
det_en
Timing
Tracker se
det_en SA
Latch&
Buffer se
Desired property: SE goes high when bitline pair has 100mV!

18. Timing Tracking Scheme
Outline
Introduction
Timing Tracking Scheme
Traditional replica-based scheme
Per-Column Timing Tracking
Experimental Results
Conclusion

19. Effect of Variation on Sense Amp. Vt
As Vt mismatch in sense amplifier becomes excessive, the probability of read failure increases.
proposal
proposed
Pass Rate
replica-based
dummy bitline
Local standard deviation of Vt for transistors in SA (mV)

20. Effect of Variation on Bitline Capacitance
Our is insensitive to bitline capacitance variation.
On the contrary, replica-based method is vulnerable.
proposed
Proposal
100fF
Pass Rate
300fF
500fF
replica-based
dummy bitline
Local standard deviation of Vt for transistors in SA (mV)

21. Layout of Test Chip Compared 1.208mm Capacitor Proposed 1.108mm
(Technology):
TSMC 0.18um CMOS 1P6M
(Creating Nanometer Effects):
We used different loadings on
different bitlines so as to mimic
the different operating speeds
in deeper nanometer technologies

22. Layout of Compared SRAM
Row decoder
Cell array
IO circuitry
Column decoder & Output buffer
Control & Input buffer &
Row address buffer
Column address buffer

23. Layout of Proposed SRAM
Row decoder
Cell array
IO circuitry & Timing tracker
Column decoder & Output buffer
Control & Input buffer &
Row address buffer
Column address buffer

24. Test Chip Characteristics
Technology
TSMC 0.18um CMOS 1P6M
Package
40-pin S/B
SRAM macro organization
32 rows x 64 columns
Test chip area
1.108 mm x mm
Power supply voltage
1.8 V
Operating Clock frequency
200 MHz
Power dissipation for compared SRAM
mW (100%)
Power dissipation for proposed SRAM
mW (136.8%)
Access time for compared SRAM
1.969 ns
Access time for proposed SRAM
2.301 ns (116.8%)

25. Conclusion Why Timing Control in an SRAM?
(1) for latch-based sense amplifier enabling
(2) for pulsed wordline control
So as to achieve lower power dissipation
Drawback of Existing Replica-Based Scheme
Replica simply cannot track every bitline pair
Proposed Per-Column Timing Tracking
Adaptive on-the-fly
More tolerant to process variation
Suitable for deeper nanometer technologies