1. Chapter 6 Arithmetic

2. Addition 0111 + 0 0 1 1 1 1 0 0 0 1101 Carry in Carry out 7 + 6 13

3. s i = c i +1 = Figure 6.1. Logic specification for a stage of binary addition. 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x i y i Carry-in c i Sum s i Carry-out c i+1 x i y i c i x i y i c i x i y i c i x i y i c i x i y i c i = + ++ y i c i x i c i x i y i + + + + DNF (disjunctive normal form)

4. Logic for a Single Stage

5. FA x n-1 cncn s n-1 y n-1 FA x0x0 c1c1 s0s0 y0y0 x1x1 C n-1 s1s1 y1y1 … c0c0 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder

6. n-bit adder X kn-1 c kn s kn-1 y kn-1 X0X0 cncn s0s0 y0y0 XnXn C n-1 S 2n-1 ynyn … c0c0 Cascade of k n-bit adders n-bit adder … S (k-1)n SnSn … … S n-1 X 2n-1 y 2n-1 … X n-1 y n-1

7. Add/Sub control n-bit adder x n1- x 1 x 0 c n s n1- s 1 s 0 c 0 y n1- y 1 y 0 Figure 6.3. Binary addition-subtraction logic network … … … …

8. FA X n-1 cncn s n-1 y n-1 FA X0X0 c1c1 s0s0 y0y0 X1X1 C n-1 s1s1 y1y1 … c0c0 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder Timing inputs result

9. Timing Gate delays –Propagation through the circuit over the longest path From x 0 …y 0 at the LSB position To c n, S n-1 at MSB C n-1 available in 2(n-1) “gate delays” S n-1 available 1 delay later C n 1 delay later –Total of 2n gate delays –+ 2 more to set overflow

10. Logic for a Single Stage 2 “gate delays” 1 “gate delay”

11. FA X n-1 cncn s n-1 y n-1 FA X0X0 c1c1 s0s0 y0y0 X1X1 C n-1 s1s1 y1y1 … c0c0 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder 2(n -1) gate delays to here 1 more gate delay to here 2n gate delays + 2 more to set “overflow”

12. Timing 2 n gate delays: n = 8, 32, 64 Need for “fast adder” Carry lookahead

13. s i = c i +1 = x i y i c i x i y i c i x i y i c i x i y i c i x i y i c i = + ++ y i c i x i c i x i y i + + + + c i+1 = x i y i + (x i + y i ) c i c i+1 = G i + P i C i where G i = x i y i and P i = x i + y i (G = “generate”P = “propagate”) c i+1 = G i + P i G i-1 + P i P i-1 c i-1 … cici

14. c i+1 = G i + P i G i-1 + P i P i-1 G i-2 + … + P i P i-1 …P 1 G 0 + P i P i-1 …P 0 C 0 Then, the expression for any carry is: For a 4-bit adder: c 0 = G 0 + P 0 c 0 c 1 = G 1 + P 1 G 0 + P 1 P 0 c 0 c 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 c 0 c 3 = G 3 + P 3 G 2 + + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 c 0

15. Bit-stage cell x i y i c i + + = G i = x i y i P i = x i + y i Same as Unless x i + y i = 1 and then G i = 1 and it doesn’t matter what P i is x i y i +

16. The “calculation” from the preceding chart 4 bits => “fan-in to last (left-most) gate is 5 -- the limit for practical application 4-bit carry-lookahead adder

17. Figure 6.5. 16-bit carry-lookahead adder built from 4-bit adders (Similarly for 32-bit or 64-bit adders) Carry-lookahead logic 4-bit adder s 15-12 P 3 I G 3 I c 12 P 2 I G 2 I c 8 s 11-8 G 1 I c 4 P 1 I s 7-4 G 0 I c 0 P 0 I s 3-0 c 16 x 15-12 y x 11-8 y x 7-4 y x 3-0 y. G 0 II P 0

18. (13) Multiplicand M 1 1 (143) Product P (11) Multiplier Q 1 0 0 1 1 1 1101 1011 0000 1011 01001111 x (a) Manual multiplication algorithm Multiplication of Positive Numbers Multiply “by hand” or programmatically

21. Uses lots of gates (transistors), lots of space on a chip (64 x 64, say) Delay--signal propagation from upper right to lower left-- for an n x n array: 6(n-1) gate delays

22. Control Sequencer n-bit adder Add/Noadd control MUX Multiplier Q m0m0 C Multiplicand M Register A (initially 0) q0q0 a0a0 m n-1 a n-1 q n-1 Sequential circuit binary multiplier (positive numbers) Shift right 0 0

23. Multiplicand in M, Multiplier in Q, A initially 0, C initially 0 C is the carry from the adder C, A and Q combined will hold the partial product LSB in Q will determine the Add/Noadd to determine if M is to be added to the partial product C, A and Q are shifted right after each add so LSB in Q always hold next multiplier bit (previous LSB is discarded) Control sequencer will shift and add n times

24. Initial configuration First cycle Second cycle Third cycle Fourth cycle C A Q 011011011Add 001101101Shift 100111101Add 010011110Shift 010011110Add 001001111Shift 100011111Add 010001111Shift M 1101 000001011 Product 13 x 11 143 Partial product

25. Signed Operands Positive multiplier and a negative multiplicand: – partial product must be sign extended (to the left as far as possible) Maintains the sign of the partial product

26. Figure 6.8. Sign extension of negative multiplicand. 1 0 1111110011 110 110 1 0 1000111011 000000 1100111 00000000 110011111 ( -13) (-143) (+11) Sign extension is shown in red

27. Negative multiplier: –Replace both numbers with their two’s complement (doesn’t change the sign of the result) Proceed as before Just add sign extension hardware to what was discussed for positive numbers Signed Operands

28. Control Sequencer n-bit adder Add/Noadd control MUX Multiplier Q m0m0 C Multiplicand M Register A (initially 0) q0q0 a0a0 m n-1 a n-1 q n-1 Sequential circuit binary multiplier (signed numbers) Shift right 0 0 Maintain a sign-extended partial product (always positive)

29. Figure 6.9. Normal multiplication scheme. 0 00 101101 0 000000 1 0 011010 1011010 1011010 1011010 0000000 000000 011000101010 0 00 1+1+1+1+

30. Multiplier 0011110 requires adding 4 shifted versions of the multiplicand 0011110 (30) can also be viewed as the difference between two numbers (32 and 2) 0100000 (32) - 0000010 (2) 0011110 (30)

31. Figure 6.9. Booth multiplication scheme. 0 1 010111 0000 00000000000000 111111101001 00 0 000101101 00000000 01100010010001 2's complement of the multiplicand 0 0 0 0 1 + 1- 0 0 0000000000 00000000 0000000

32. Figure 6.10. Booth recoding of a multiplier. 001101011100110100 00000000 1+1-1-1+1-1+1-1+1-1+

33. Multiplier Biti i 1 - Version of multiplicand selected by biti 0 1 0 0 01 11 0M  1+M  1  M  0M  Figure 6.12. Booth multiplier recoding table.

34. Figure 6.13. Booth recoded multipliers. 1 0 1110000111110000 001111011010001 101010101010101 0 000000000000 00000000 1-1-1-1-1-1-1-1- 1-1-1-1- 1-1- 1+1+1+1+1+1+1+1+ 1+ 1+1+1+ 1+ Worst-case multiplier Ordinary multiplier Good multiplier

35. Figure 6.20. Longhand division examples. 1101 1 13 14 26 21 274100010010 10101 1101 1 1110 1101 10000 13 1101

36. Divisor M n-bit adder Control Sequencer Shift left Dividend Q Quotient setting Add/Subtract Circuit for binary division

37. Division n times: 1) Shift A and Q left 1 2) Subtract M from A, result in A 3) –if sign of A is 1, set q 0 to 0 and add M back to A (restore A –otherwise set q 0 to 1

38. Floating Point Representation Need for more than just (say) 32-bit integers –Need larger numbers –Need fractions (some very small) Integers –d 31, d 30, …. d 0.The binary point or –. d 31, d 30, …. d 0 The binary point

39. Neither is satisfactory Need the binary point to “float” Scientific notation.123451.234 x 10 -2 1234.51.234 x 10 3 12.3451.234 x 10 Floating Point Representation

40. An E of 0 means 2 -127 E of 127 means 2 0 E of 255 means 2 128 IEEE standard (Intel and other processors conform) binary point

41. Normalization and the “hidden bit” 0 10001000 0010110… 0 10000101 010110… 0.0010110… x 2 9 1.0110… x 2 6 the “hidden bit” (always a 1) Unnormalized: Normalized:

42. Single precision: ~7 decimal digits of “precision” (7 significant digits) in range 2 -127 to 2 128 (or 10 -38 to 10 38 ) Double precision:~16 decimal digits in range 2 -1022 to 2 1023 (or 10 -308 to 10 308 )

43. Special Values E = 0M = 0value is 0 E = 255M = 0value is “infinity” (result of divide by 0) E = 0 M /= 0“denormal numbers” smaller than the smallest “normal number” gradual underflow E = 255M /= 0NaN result of an invalid operation(undefined) e.g., 0/0, sqrt(-1)