1. Sequential Logic Review
The R/S Latch
Illegal states and race conditions
Clocked Latches
Master-Slave Flip-Flop
The One’s-Catching Problem
The D Flip-Flop
Setup and Hold Constraints
Finite-State Machine Design
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2. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 2
The R/S Latch
R=1, S=0 => D=1
R=0, S=1 => D=0
R=0, S=0 => D unchanged
R=1, S = 1 =>
Race Condition happens when “HOLD” Condition follows illegal state
Outputs oscillate between 0 and 1
In practice, settles down to unpredictable state (01 or 10; can’t tell which)
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3. R/S Latch State Diagram
Non-determinism leads to race condition
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4. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 4
Clocked R/S Latch
Add Clock, two NOR gates to R/S Latch
When Clock is high, R=S=0
State Held
S/R only when Clk low
Key constraint: S’, R’ unchanging when Clk is low
Illegal input still possible
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5. Clocking Constraint for cascaded latches
Minimum propagation delay through logic must be greater than clock period
Otherwise values race through latches R S Q Q’
Logic R S Q Q’
Clk
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6. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 6
Master-Slave Latch
Two latches, back-to-back
Enabled by different clocks
Key: “Slave” only active when “Master” inactive
Can be safely combined without timing constraints
Key Problem “1’s Catch”
Clk
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7. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 7
1’s Catching Problem
Clk is high, R=S=0
Glitch: R:0®1®0
0®1 Sets master to high
1®0 holds Q (holds 1)
Clk goes low, propagating 1 to slave!
Glitch is caught as value of R/S
Clk
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8. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 8
D Flip-Flop
Three Latches
Top Latch holds D’ when clock is low
Bottom latch holds D when clock is low
Front latch is output
Avoids 1’s catching problem
Avoids illegal states, race conditions
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9. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 9
D Flip-Flop
Clk = 1
Clk = 0 D D D’ D D’ D’
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10. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 10
Key Feature of D FF
Input must be stable near clock edge
Tsu: Setup time. Minimum time input stable before clock edge
Th: Hold time. Minimum time input stable after clock edge
Failure to meet constraints means improper operation
Setup Violation
(1 may be latched in) D
Tsu
Clk
Clk Th
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11. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 11
Clocking Constraints
Tp: propagation delay through FF
Tperiod: Clock period
Th: hold time (time input must be stable after clock edge)
Tsu: setup time (time input must be stable before clock edge)
Delay for output transition must be greater than hold time
Th < Tp
Setup time + propagation delay must be less than clock period
Tsu + Tp < Tperiod
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12. Basic Abstraction of Sequential Logic
reg
Logic
for
outputs
outputs
Logic
inputs
Combinational
Logic for
Next State
Logic
for
outputs
reg
outputs
state feedback
Abstraction
Implementation
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13. Simple Sequential Logic
Shift Registers
Counters
Covered extensively last time
Little or no combinational logic
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14. Finite-State Machines
Logic
for
outputs
outputs
inputs
Combinational
Logic for
Next State
Logic
for
outputs
reg
outputs
inputs
Combinational
Logic for
Next State
Logic
for
outputs
state feedback
reg
outputs
Mealy
(Output Function of Inputs and States)
state feedback
Moore
(Output Function of States)
Key Distinction: Latch on every path from input to output
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15. Sequential Logic Implementation
Models for representing sequential circuits
Abstraction of sequential elements
Finite state machines and their state diagrams
Inputs/outputs
Mealy, Moore, and synchronous Mealy machines
Finite state machine design procedure
Verilog specification
Deriving state diagram
Deriving state transition table
Determining next state and output functions
Implementing combinational logic
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16. Mealy vs. Moore Machines
Moore: outputs depend on current state only
Mealy: outputs depend on current state and inputs
Ant brain is a Moore Machine
Output does not react immediately to input change
We could have specified a Mealy FSM
Outputs have immediate reaction to inputs
As inputs change, so does next state, doesn’t commit until clocking event A
L’ R’ / TR, F
L / TL
L’ R / TL, F
react right away to leaving the wall
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17. Specifying Outputs for a Moore Machine
Output is only function of state
Specify in state bubble in state diagram
Example: sequence detector for 01 or 10
current next reset input state state output
1 – – A
0 0 A B 0
0 1 A C 0
0 0 B B 0
0 1 B D 0
0 0 C E 0
0 1 C C 0
0 0 D E 1
0 1 D C 1
0 0 E B 1
0 1 E D 1
D/1
E/1
B/0
A/0
C/0 1
reset
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18. Specifying Outputs for a Mealy Machine
Output is function of state and inputs
Specify output on transition arc between states
Example: sequence detector for 01 or 10
current next reset input state state output
1 – – A 0
0 0 A B 0
0 1 A C 0
0 0 B B 0
0 1 B C 1
0 0 C B 1
0 1 C C 0 B A C
0/1
0/0
1/1
1/0
reset/0
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19. Comparison of Mealy and Moore Machines
Mealy Machines tend to have less states
Different outputs on arcs (n^2) rather than states (n)
Moore Machines are safer to use
Outputs change at clock edge (always one cycle later)
In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback
Mealy Machines react faster to inputs
React in same cycle – don't need to wait for clock
In Moore machines, more logic may be necessary to decode state into outputs – more gate delays after
Logic
for
outputs
inputs
Combinational
Logic for
Next State
inputs
outputs
Logic
for
outputs
reg
outputs
Combinational
logic for
Next State
reg
state feedback
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state feedback

20. Mealy and Moore Examples
Recognize A,B = 0,1
Mealy or Moore?
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21. Mealy and Moore Examples (cont’d)
Recognize A,B = 1,0 then 0,1
Mealy or Moore?
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22. Registered Mealy Machine (Really Moore)
Synchronous (or registered) Mealy Machine
Registered state AND outputs
Avoids ‘glitchy’ outputs
Easy to implement in programmable logic
Moore Machine with no output decoding
Outputs computed on transition to next state rather than after entering
View outputs as expanded state vector
output logic
Outputs
Inputs
next state logic
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Current State

23. Verilog FSM - Reduce 1s Example
Change the first 1 to 0 in each string of 1’s
Example Moore machine implementation 1
zero [0]
one1 [0]
two1s
[1]
// State assignment
parameter zero = 0, one1 = 1, two1s = 2;
module reduce (out, clk, reset, in); output out; input clk, reset, in; reg out; reg [1:0] state; // state register reg [1:0] next_state;
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24. Moore Verilog FSM (cont’d)
or state) case (state)
zero: begin // last input was a zero out = 0; if (in) next_state = one1; else next_state = zero; end
one1: begin // we've seen one out = 0; if (in) next_state = two1s; else next_state = zero; end
two1s: begin // we've seen at least 2 ones out = 1; if (in) next_state = two1s; else next_state = zero; end
default: begin // in case we reach a bad state
out = 0;
next_state = zero;
endcase 1
zero [0]
one1 [0]
two1s
[1]
include all signals
that are input to state
and output equations
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25. Moore Verilog FSM (cont’d)
// Implement the state register
clk) if (reset) state <= zero; else state <= next_state;
endmodule 1
zero [0]
one1 [0]
two1s
[1]
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26. Mealy Verilog FSM for Reduce-1s Example
module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register
reg next_state;
parameter zero = 0, one = 1;
or state) case (state) zero: begin // last input was a zero if (in) next_state = one; else next_state = zero;
out = 0; end one: // we've seen one if (in) begin next_state = one;
out = 1; end else begin
next_state = zero;
out = 0; end endcase
clk)
if (reset) state <= zero; else state <= next_state; endmodule
1/0
0/0
1/1
zero
one1
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27. Synchronous Mealy Verilog FSM for Reduce-1s Example
module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register
reg next_state; reg next_out;
parameter zero = 0, one = 1;
or state) case (state) zero: begin // last input was a zero if (in) next_state = one; else next_state = zero;
next_out = 0; end one: // we've seen one if (in) begin next_state = one;
next_out = 1; end else begin
next_state = zero;
next_out = 0; end endcase
clk)
if (reset) begin
state <= zero; out <= 0;
end
else begin
state <= next_state; out <= next_out;
endmodule
1/0
0/0
1/1
zero
one1
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28. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 28
Announcements
First Midterm, Tuesday, 26 February, 2-3:30 PM, 125 Cory Hall
No calculators or other gadgets are necessary! Don’t bring them! No blue books! All work on the sheets handed out!
Do bring pencil and eraser please! If you like to unstaple the exam pages, then bring a stapler with you! Write your name and student ID on EVERY page in case they get separated -- it has happened!
Don’t forget your two-sided 8.5” x 11” crib sheet!
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29. CS 150 - Spring 2008 – Lec #7: Sequential Implementation – 29
Announcements
Examination, Tue, 2-3:30 PM, 125 Cory Hall
Topics likely to be covered
Combinational logic: design and optimization (K-maps up to and including 6 variables)
Implementation: Simple gates (minimum wires and gates), PLA structures (minimum unique terms), Muxes, Decoders, ROMs, (Simplified) Xilinx CLB
Sequential logic: R-S latches, flip-flops, transparent vs. edge-triggered behavior, master/slave concept
Basic Finite State Machines: Representations (state diagrams, transition tables), Moore vs. Mealy Machines, Shifters, Registers, Counters
Structural and Behavioral Verilog for combinational and sequential logic
Labs 1, 2, 3
K&B: Chapters 1, 2 ( ), 3 (3.1, 3.6), 4 (4.1, 4.2, 4.3), 6 (6.1, 6.2.1, 6.3), 7 (7.1, 7.2, 7.3)
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30. Example: Vending Machine
Release item after 15 cents are deposited
Single coin slot for dimes, nickels
No change
Reset N
Vending Machine FSM
Open
Coin Sensor
Release Mechanism D
Clock
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31. Example: Vending Machine (cont’d)
Suitable Abstract Representation
Tabulate typical input sequences:
3 nickels
nickel, dime
dime, nickel
two dimes
Draw state diagram:
Inputs: N, D, reset
Output: open chute
Assumptions:
Assume N and D asserted for one cycle
Each state has a self loop for N = D = 0 (no coin) S0
Reset S1 N S2 D S3 N S4
[open] D S5
[open] N S6
[open] D S7
[open] N
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32. Example: Vending Machine (cont’d)
Minimize number of states - reuse states whenever possible 0¢
Reset
symbolic state table
present inputs next output state D N state open 0¢ ¢ ¢ ¢ – – 5¢ ¢ ¢ ¢ – – 10¢ ¢ ¢ ¢ – – 15¢ – – 15¢ 1
10¢ D 5¢ N
15¢
[open] D N
N + D
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33. Example: Vending Machine (cont’d)
Uniquely Encode States
present state inputs next state output Q1 Q0 D N D1 D0 open – – – – – – – – – – –
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34. Example: Vending Machine (cont’d)
Mapping to Logic
X X X X Q1 D1 Q0 N D D0
Open
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
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35. Example: Vending Machine (cont’d)
One-hot Encoding
present state inputs next state output Q3 Q2 Q1 Q0 D N D3 D2 D1 D0 open
D0 = Q0 D’ N’
D1 = Q0 N + Q1 D’ N’
D2 = Q0 D + Q1 N + Q2 D’ N’
D3 = Q1 D + Q2 D + Q2 N + Q3
OPEN = Q3
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36. Equivalent Mealy and Moore State Diagrams
Moore machine
outputs associated with state
Mealy machine
outputs associated with transitions 0¢
[0]
10¢ 5¢
15¢
[1]
N’ D’ + Reset D N
N+D
N’ D’
Reset’
Reset 0¢
10¢ 5¢
15¢
(N’ D’ + Reset)/0
D/0
D/1
N/0
N+D/1
N’ D’/0
Reset’/1
Reset/0
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37. Moore Verilog FSM for Vending Machine
module vending (open, Clk, Reset, N, D); input Clk, Reset, N, D; output open; reg open; reg state; // state register
reg next_state;
parameter zero = 0, five = 1, ten = 2, fifteen = 3;
or D or state) case (state) zero: begin if (D) next_state = five; else if (N) next_state = ten;
else next_state = zero;
open = 0; end …
fifteen: begin
if (!Reset) next_state = fifteen;
open = 1;
end endcase
clk)
if (Reset || (!N && !D)) state <= zero; else state <= next_state; endmodule 0¢
[0]
10¢ 5¢
15¢
[1]
N’ D’ + Reset D N
N+D
N’ D’
Reset’
Reset
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38. Mealy Verilog FSM for Vending Machine
module vending (open, Clk, Reset, N, D); input Clk, Reset, N, D; output open; reg open; reg state; // state register
reg next_state; reg next_open;
parameter zero = 0, five = 1, ten = 2, fifteen = 3;
or D or state) case (state) zero: begin if (D) begin
next_state = ten; next_open = 0;
end
else if (N) begin
next_state = five; next_open = 0;
else begin
next_state = zero; next_open = 0;
end end …
endcase
clk)
if (Reset || (!N && !D)) begin state <= zero; open <= 0; end
else begin state <= next_state; open <= next_open; end endmodule 0¢
10¢ 5¢
15¢
(N’ D’ + Reset)/0
D/0
D/1
N/0
N+D/1
N’ D’/0
Reset’/1
Reset/0
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39. Example: Traffic Light Controller
A busy highway is intersected by a little used farmroad
Detectors C sense the presence of cars waiting on the farmroad
with no car on farmroad, light remain green in highway direction
if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green
these stay green only as long as a farmroad car is detected but never longer than a set interval
when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green
even if farmroad vehicles are waiting, highway gets at least a set interval as green
Assume you have an interval timer that generates:
a short time pulse (TS) and
a long time pulse (TL),
in response to a set (ST) signal.
TS is to be used for timing yellow lights and TL for green lights
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40. Example: Traffic Light Controller (cont’d)
Highway/farm road intersection
farm road
car sensors
highway
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41. Example: Traffic Light Controller (cont’d)
Tabulation of Inputs and Outputs inputs description outputs description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired
Tabulation of unique states – some light configurations imply others state description S0 highway green (farm road red) S1 highway yellow (farm road red) S2 farm road green (highway red) S3 farm road yellow (highway red)
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42. Example: Traffic Light Controller (cont’d)
State Diagram
Reset
(TL•C)' S0
TS / ST
S0: HG
S1: HY
S2: FG
S3: FY
TL•C / ST S1 S3
TS'
TS'
TS / ST
TL+C' / ST S2
(TL+C')'
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43. Example: Traffic Light Controller (cont’d)
Generate state table with symbolic states
Consider state assignments
output encoding – similar problem to state assignment (Green = 00, Yellow = 01, Red = 10)
Inputs Present State Next State Outputs C TL TS ST H F 0 – – HG HG 0 Green Red – 0 – HG HG 0 Green Red 1 1 – HG HY 1 Green Red – – 0 HY HY 0 Yellow Red – – 1 HY FG 1 Yellow Red 1 0 – FG FG 0 Red Green 0 – – FG FY 1 Red Green – 1 – FG FY 1 Red Green – – 0 FY FY 0 Red Yellow – – 1 FY HG 1 Red Yellow
SA1: HG = 00 HY = 01 FG = 11 FY = 10 SA2: HG = 00 HY = 10 FG = 01 FY = 11 SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot)
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44. Traffic Light Controller Verilog
Reset
TS'
TS / ST
(TL•C)'
TL•C
(TL+C')'
TL+C' / ST S0 S2 S3 S1
module traffic (ST, Clk, Reset, C, TL, TS);
input Clk, Reset, C, TL, TS; output ST;
reg ST; reg state;
reg next_state; reg next_ST;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
or TL or TS or state)
case (state)
S0: if (!(TL && C)) begin
next_state = S0; next_ST = 0;
else if (TL || C) begin
next_state = S1; next_ST = 1;
end …
endcase
Clk)
if (Reset) begin state <= S0; ST <= 0; end
else begin state <= next_state; ST <= next_ST; end endmodule
TL+C / ST
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45. Logic for Different State Assignments
SA1 NS1 = C•TL'•PS1•PS0 + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0 NS0 = C•TL•PS1'•PS0' + C•TL'•PS1•PS0 + PS1'•PS0 ST = C•TL•PS1'•PS0' + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0 H1 = PS1 H0 = PS1'•PS0 F1 = PS1' F0 = PS1•PS0'
SA2 NS1 = C•TL•PS1' + TS'•PS1 + C'•PS1'•PS0 NS0 = TS•PS1•PS0' + PS1'•PS0 + TS'•PS1•PS0 ST = C•TL•PS1' + C'•PS1'•PS0 + TS•PS1 H1 = PS0 H0 = PS1•PS0' F1 = PS0' F0 = PS1•PS0
SA3 NS3 = C'•PS2 + TL•PS2 + TS'•PS3 NS2 = TS•PS1 + C•TL'•PS2 NS1 = C•TL•PS0 + TS'•PS1 NS0 = C'•PS0 + TL'•PS0 + TS•PS3 ST = C•TL•PS0 + TS•PS1 + C'•PS2 + TL•PS2 + TS•PS3 H1 = PS3 + PS2 H0 = PS1 F1 = PS1 + PS0 F0 = PS3
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46. Vending Machine Example Revisted (PLD mapping)
D0 = reset'(Q0'N + Q0N' + Q1N + Q1D)
D1 = reset'(Q1 + D + Q0N)
OPEN = Q1Q0
CLK D Q Q0 N D Q Q1 D D Q
Open
Reset
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47. Vending Machine (cont’d)
OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change
Clock cycle to set Q1 and Q0 THEN a gate delay THEN an
This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay
OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
Implementation now looks like a Mealy machine
Common for programmable devices to have FF at end of logic
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48. Vending Machine (Retimed PLD Mapping)
OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
CLK D Q Q0 N D Q Q1 D
OPEN D Q
Open
Reset
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49. Sequential Logic Implementation Summary
Models for representing sequential circuits
Abstraction of sequential elements
Finite state machines and their state diagrams
Inputs/outputs
Mealy, Moore, and synchronous Mealy machines
Finite state machine design procedure
Verilog specification
Deriving state diagram
Deriving state transition table
Determining next state and output functions
Implementing combinational logic
CS Spring – Lec #7: Sequential Implementation – 49