1. www.eecs.umich.edu/~sdrg 1 SODA: A Low-power Architecture For Software Radio Yuan Lin 1, Hyunseok Lee 1, Mark Woh 1, Yoav Harel 1, Scott Mahlke 1, Trevor Mudge 1, Chaitali Chakrabarti 2, Krisztian Flautner 3 1 Advanced Computer Architecture Lab, University of Michigan 2 Department of Electrical Engineering, Arizona State University 3 ARM, Ltd.

2. www.eecs.umich.edu/~sdrg 2 Anatomy of 3G Cellular Phone

3. www.eecs.umich.edu/~sdrg 3 Advantages of Software Defined Radio Multi-mode operations Lower costs –Faster time to market –Prototyping and bug fixes –Chip volumes –Longevity of platforms Protocol complexity favors software dominated solutions Enables future wireless communication innovations –Cognitive radio

4. www.eecs.umich.edu/~sdrg 4 Why is SDR Challenging? SDR Design Objectives for 3G and WiFi –Throughput requirements 40Gops peak throughput –Power budget 100mW~500mW peak power

5. www.eecs.umich.edu/~sdrg 5 The Anatomy of Wireless Protocols 1. Filtering: suppress signals outside frequency band 2. Modulation: map source information onto signal waveforms 3. Channel Estimation: Estimate channel condition for transceivers 4. Error Correction: correct errors induced by noisy channel

6. www.eecs.umich.edu/~sdrg 6 SDR – Application Specific Design Wireless protocols are systems of DSP algorithms –System-level Example: Specification of W-CDMA DCH channel –Algorithm-level Example: Implementation of a 64 point FFT

7. www.eecs.umich.edu/~sdrg 7 System Level Design Decisions System CharacteristicsSODA Architectural Decisions 1. Algorithm macro-pipelining with streaming computation 1. Multi-core system 2. Communication through DMA 2. Multiple periodic real-time deadlines 3. Deterministic hardware behavior 4. Compile-time algorithm mapping and scheduling 3. Low streaming throughput between algorithms 5. Low throughput interconnect 4. Heterogeneous inter- algorithm communication 6. Multi-level scratchpad memories

8. www.eecs.umich.edu/~sdrg 8 SODA System Architecture 4 PEs –static kernel mapping and scheduling –SIMD+Scalar units 1 ARM GPP controller –scalar algorithms and protocol controls

9. www.eecs.umich.edu/~sdrg 9 SODA Memory Organization 2-Level scratchpad memories –12KB Local scratchpad memory for stream queues –64KB global scratchpad memory for large buffers Low-throughput shared bus –200MHz 32-bit bus –inter-PE communication using DMA

10. www.eecs.umich.edu/~sdrg 10 DSP Algorithm Characteristics 8 to 16-bit precision Vector operations –long vectors –constant vector size Static data movement patterns Scalar operations AlgorithmsType of Computation Vector Width W-CDMA FilterVector64 ModulationVector2560 Channel Est.Vector320 Error CorrectionMixed8 or 256 802.11a FilterVector33 Modulation (FFT)Vector64 Channel Est.Mixed16 Error CorrectionMixed64

11. www.eecs.umich.edu/~sdrg 11 SODA PE Architecture

12. www.eecs.umich.edu/~sdrg 12 SODA PE SIMD Pipeline

13. www.eecs.umich.edu/~sdrg 13 SODA PE SIMD Pipeline

14. www.eecs.umich.edu/~sdrg 14 SODA PE SIMD Shuffle Network

15. www.eecs.umich.edu/~sdrg 15 SODA PE Scalar Pipeline

16. www.eecs.umich.edu/~sdrg 16 W-CDMA Mapping On SODA

17. www.eecs.umich.edu/~sdrg 17 SDR Performance Distribution 802.11a has higher number of total computational cycles W-CDMA requires higher computational cycles per bit

18. www.eecs.umich.edu/~sdrg 18 Power Consumption at 180nm Wide SIMD requires higher number of pipeline registers 802.11a consumes higher power than W-CDMA 8-bit W-CDMA computation versus 16-bit 802.11a computation

19. www.eecs.umich.edu/~sdrg 19 Summary Key features of SODA –Multi-PE with scratchpad memories –Low throughput shared bus –2-issue LIW: SIMD+(Scalar or AGU) –32-wide SIMD processing –SIMD shuffle network SDR Hardware RequirementsSODA Results Comp. requirements: 10 ~ 100 GOPS W-CDMA & 802.11a: 1.3 ~ 2 GOPS (with SODA LIW ops) Sub-watt power budget: ~ 0.2 Watt for cellular phones 180nm: ~ 3 Watts (area: 26.6mm 2 ) 90nm (est.): ~ 0.5 Watt (6.7 mm 2 )

20. www.eecs.umich.edu/~sdrg 20 Conclusion & Future Work Conclusion –2G and 3G SDR solutions are achievable in 90nm –Optimization opportunities at the algorithm, software and hardware levels Future Work –SDR for Idle mode operation (ISLPED ’06) –SODA for 4G protocols –Application-specific language for SDR –Compiler for SODA

21. www.eecs.umich.edu/~sdrg 21 Questions? www.eecs.umich.edu/~sdrg

22. 22 Backup Slides

23. www.eecs.umich.edu/~sdrg 23 Different Levels of Software Radio TierNameDescription Tier 0 Hardware Radio (HR) Implemented using hardware components. Cannot be modified Tier 1 Software Controlled Radio (SCR) Only control functions are implemented in software: inter-connects, power levels, etc. Tier 2 Software Defined Radio (SDR) Software control of a variety of modulation techniques, wide-band or narrow-band operation, security functions, etc. Tier 3 Ideal Software Radio (ISR) Programmability extends to the entire system with analog conversion only at the antenna. Tier 4 Ultimate Software Radio (USR) Defined for comparison purposes only

24. www.eecs.umich.edu/~sdrg 24 Power Methodology Our flow sequence was –Design Compiler and Silicon Ensemble For Initial Floorplan Estimation –Physical Compiler For placement and Optimization –Silicon Ensemble Routing We optimized for power and delay Blocks like memory were generated with Artisan Memory Generators We used the Synopsys IP Blocks as much as possible to get better compiled blocks

25. www.eecs.umich.edu/~sdrg 25