1. 1 Logic synthesis from concurrent specifications Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain In collaboration with M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev

2. 2 Outline Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit Complex gates Complex gates C-element architecture C-element architecture Review of some advanced topics

3. 3 Book and synthesis tool J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic synthesis for asynchronous controllers and interfaces, Springer-Verlag, 2002 petrify: http://www.lsi.upc.es/petrify

4. 4 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

5. 5 x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z Specification

6. 6 x y z x+ x- y+ y- z+ z- Token flow

7. 7 x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y- State graph

8. 8 Next-state functions xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y-

9. 9 x z y Gate netlist

10. 10 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

11. 11 VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

12. 12 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

13. 13 Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- DTACK- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- DTACK- LDS- LDTACK-

14. 14 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw-

15. 15 Circuit synthesis Goal: Derive a hazard-free circuit under a given delay model and mode of operation Derive a hazard-free circuit under a given delay model and mode of operation

16. 16 Speed independence Delay model Unbounded gate / environment delays Unbounded gate / environment delays Certain wire delays shorter than certain paths in the circuit Certain wire delays shorter than certain paths in the circuit Conditions for implementability: Consistency Consistency Complete State Coding Complete State Coding Persistency Persistency

17. 17 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

18. 18 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

19. 19 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

20. 20 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+ 10000 10010 10110 0111001110 01100 00110 10110 (DSr, DTACK, LDTACK, LDS, D)

21. 21 QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

22. 22 Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1  1 10110

23. 23 Karnaugh map for LDS DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 000000/1? 1 111 - - - --- ---- - ---- ---

24. 24 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

25. 25 Concurrency reduction LDS- LDS+ LDS- 10110 DSr+

26. 26 Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

27. 27 State encoding conflicts LDS- LDTACK- LDTACK+ LDS+ 10110

28. 28 Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC+ 101101 101100

29. 29 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

30. 30 Complex-gate implementation

31. 31 Implementability conditions Consistency Rising and falling transitions of each signal alternate in any trace Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) Next-state functions correctly defined Next-state functions correctly definedPersistency No event can be disabled by another event (unless they are both inputs) No event can be disabled by another event (unless they are both inputs)

32. 32 Implementability conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

33. 33 Persistency 100000001 a- c+ b+b+ b+b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

34. a+ b+ c+ d+ a- b- d- a+ c-a- 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+

35. 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 ER(d+) ER(d-)

36. ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ Complex gate

37. 37 Implementation with C elements C R S z  S+  z+  S-  R+  z-  R-  S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-)  QR(z-) R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

38. ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d

39. 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d but...

40. 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch)

41. ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Monotonic covers

42. 42 C-based implementations C S R d C d a b c a b c d weak a c d generalized C elements (gC) weak

43. 43 Speed-independent implementations Implementability conditions Consistency Consistency Complete state coding Complete state coding Persistency Persistency Circuit architectures Complex (hazard-free) gates Complex (hazard-free) gates C elements with monotonic covers C elements with monotonic covers......

44. 44 Synthesis exercise y- z-w- y+x+ z+ x- w+ 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Derive circuits for signals x and z (complex gates and monotonic covers)

45. 45 Synthesis exercise 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz 00011110 00 01 11 10 - - - - Signal x 1 0 1 1 1 1 1 0 0 0 0 0

46. 46 Synthesis exercise 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz 00011110 00 01 11 10 - - - - Signal z 1 0 0 0 0 1 1 1 0 0 0 0

47. 47 y- z-w- y+x+ z+ x- w+ 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Logic decomposition: example

48. 48 yz=1 yz=0 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ C C x y x y w z x y z y z w z w z y Logic decomposition: example

49. 49 s- s+ s- s=1 s=0 10011011 1000 1010 0111 0011 y+ x- w+ z+ z- 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 C C x y x y w z x y z w z w z y s y- Logic decomposition: example

50. 50 y- z-w- y+x+ z+ x- w+ s- s+ s- s+ s- s=1 s=0 10011011 1000 1010 0111 0011 y+ x- w+ z+ z- 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 y- Logic decomposition: example

51. 51 Speed-independent Netlist LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK csc map

52. 52 Adding timing assumptions LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK csc map LDTACK- before DSr+ FAST SLOW

53. 53 Adding timing assumptions DTACK D DSr LDS LDTACK csc map LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDTACK- before DSr+

54. 54 State space domain LDTACK- before DSr+ LDTACK- DSr+

55. 55 State space domain LDTACK- before DSr+ LDTACK- DSr+

56. 56 State space domain LDTACK- before DSr+ LDTACK- DSr+ Two more unreachable states

57. 57 Boolean domain DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 000000/1? 1 111 - - - --- ---- - ---- ---

58. 58 Boolean domain DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 00-001 1 111 - - - --- ---- - ---- --- One more DC vector for all signalsOne state conflict is removed

59. 59 Netlist with one constraint LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK csc map

60. 60 Netlist with one constraint LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK LDTACK- before DSr+ TIMING CONSTRAINT

61. 61 Conclusions STGs have a high expressiveness power at a low level of granularity (similar to FSMs for synchronous systems) Synthesis from STGs can be fully automated Synthesis tools often suffer from the state explosion problem (symbolic techniques are used) The theory of logic synthesis from STGs can be found in: J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces, Springer Verlag, 2002.