1. Presenter: Shao-Jay Hou

2. This paper introduces a new unobtrusive and cost-effective method for the capture and compression of program execution traces in real-time, which is based on a double move-to-front transformation. We explore its effectiveness and describe a cost-effective hardware implementation. The proposed trace compressor requires only 0.12 bits per instruction of trace port bandwidth, at the cost of 25K gates.

3. Continual growth in the complexity of SoC makes traditional approaches infeasible or impractical.  In-Circuit-Emulator (ICE) 。 Invasively,have to stop the processor  Software approach 。 Use breakpoint Software step-by-step debug waste too much time. There are another tracing system, but the cost or the area is to high.  C.F.Kao’s LZ-based program trace.

4. My thesis(ideal) An Embedded Infrastructure of Debug and Trace Interface for the DSP Platform A Real-Time Program Trace Compressor Utilizing Double Move-to-Front Method The application of tracer. The improve of tracer.

5. This paper ARM ETM[1] Altera Nios II[2] Xilinx Microblaze[3] Lauterbach[4] The program trace system for each embedded system processor [5-7] Another program trace system and compression techniques Mibench[8] For the experiment benchmark SimpleScalar[9] To collect the symbols in system MTF[10] Bzip2[11] The basic MTF method and bzip compression CAM[12] Hardware architecture

6. For each instruction, there are two characteristics:  SA(staring address)  SL(stream length)  PC(program counter) If the current PC is differ form the previous PC than the instruction length, the current instruction is the beginning of a new stream. The unconditional direct branch we do not terminate the current stream because the address of the next instruction in sequence can be inferred directly from the binary.

7. Some parameters in this method:  Ht(history table)  Input  Output A easy example to explain it:  If the history table ht=[C,B,A]  The input is {AABC}  The output should be 2022

9. Use two-level history table  Mtf1  Mtf2 The flow of DMTF:

10. The output bits of DMTF:  Mtf2.zhr=>mtf2 zero entry hit rate  Mtf2.ohr=>mtf2 non-zero entry hit rate  Mtf1.hr=>mtf1 hit rate  Mtf1.size=>mtf1 size  Mtf2. size=> mtf2 size

11. Am example of DMTF

12. The result of DMTF

13. Last-Value Predictor for Upper Address Bits:  Upper bits of SA in stream is rarely change during program execution  Use SA[31:20] as HLV Zero Hit Trace Counters:  Mtf2 zero entry hit happen often  Use a counter to count and dynamically adjust the size of ZLC  Use a head bit “0”

14. The block diagram of enhance DMTF trace format:

15.  bDMTF = basic DMTF  hDMTF = DMTF with HLV  eDMTF = enhance DMTF

16.  content addressable memory (CAM)  most-recently used (MRU) stack  the gates count of DMTF(192,4) is less then 24600

17. The paper present a double move-to-front method, and the compression ratio is between 82.7:1~29389:1(average is 268:1) and the bandwidth is 0.001 to 0.39 bits/instruction (average is 0.12) And the hardware is area-save  Compare to C.F.Kao[5], the area is half.

18. The paper give a good method in compression. And the paper use many example to show the method how to run. But the paper didn’t talk too much on how to experiment, and how to get the data.