1. A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006

2. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit: 0 – 4095 Successive Approximation

3. Method of Successive Approximation

4. Implementing Successive Approximation

6. A/D CPLD Control

7. Use Mealy Machine Inputs to C1: adstart, gt, done Outputs from C2: sarald, sh, adld, msel, adflg

8. A/D Control Unit Why won't this work?

9. Note: sar must be 1000 on reset so that gt can be set properly. Now we don't need the mux or the AND gates!

10. sarld sarReg maskR sar gt 0 0000 1000 1000 1 1 1000 0100 1100 0 0 1000 0010 1010 1 1 1010 0001 1011 0 0 1010 0000 1010

11. A Mealy state machine

12. ADctl

13. A Mealy state machine Use one-hot encoding: one flip-flop per state

14. module DFF (D, clk, clr, Q); input clk, clr ; wire clk, clr ; input D ; wire D ; output Q ; reg Q ; always @(posedge clk or posedge clr) if(clr == 1) Q <= 0; else Q <= D; endmodule

15. module DFF1 (D, clk, reset, Q); input clk, reset; wire clk, reset ; input D ; wire D ; output Q ; reg Q ; always @(posedge clk or posedge reset) if(reset == 1) Q <= 1; else Q <= D; endmodule

16. // adconv control module ADctrl(Clk, Clear, gt, adstart, done, sarld, sh, adld, adflg); input Clk, Clear, gt, adstart, done; output sarld, sh, adld, adflg; wire msel, sarld, sh, adld, adflg; wire start, keep, remove; wire startD, keepD, removeD; assign startD = start & ~adstart | keep & done | remove & done; assign keepD = start & adstart & gt | keep & gt & ~done | remove & gt & ~done; assign removeD = start & adstart & ~gt | keep & ~gt & ~done | remove & ~gt & ~done;

17. DFF1 startFF(.D(startD),.clk(Clk),.reset(Clear),.Q(start)); DFF keepFF(.D(keepD),.clk(Clk),.clr(Clear),.Q(keep)); DFF removeFF(.D(removeD),.clk(Clk),.clr(Clear),.Q(remove));

18. // C2 Outputs assign adflg = done; assign adld = done; assign sarld = gt & keep | gt & remove | gt & adstart & start; assign sh = ~done & keep | ~done & remove | adstart & start; endmodule

19. // Title : A/D converter module adconv(clock, clear, adstart, gt, adflg, sar, adreg); input clock, clear, adstart, gt; output adflg; output [3:0] sar, adreg; wire adflg, sarld, adld, sh, done; wire [3:0] sar, adreg; ADpath adc1(.clk(clock),.reset(clear),.sh(sh),.sarld(sarld),.adld(adld),.sar(sar),.ADR(adreg),.done(done)); ADctrladc2(.Clk(clock),.Clear(clear),.gt(gt),.adstart(adstart),.done(done),.sarld(sarld),.sh(sh),.adld(adld),.adflg(adflg)); endmodule

20. A Mealy state machine Use binary encoding: two flip-flops

21. // adconv control module ADctrl(Clk, Clear, gt, adstart, zero, msel, sarld, sh, adld, adflg); input Clk, Clear, gt, adstart, zero; output sarld, sh, adld, adflg; reg msel, sarld, sh, adld, adflg; reg[2:0] present_state, next_state; parameterstart = 2'b00, keep = 2'b01, remove = 2'b11;

22. always @(posedge Clk or posedge Clear) begin if (Clear == 1) present_state <= start; else present_state <= next_state; end

23. always @(present_state or adstart or gt or done) begin case(present_state) start: if(adstart == 1) next_state <= load; else if(gt == 1) next_state <= keep; else next_state <= remove; keep: if(done == 1) next_state <= start; else if(gt == 1) next_state <= keep; else next_state <= remove; remove: if(done == 1) next_state <= start; else if(gt == 1) next_state <= keep; else next_state <= remove; default next_state <= start; endcase end

24. // C2 Outputs assign adflg = done; assign adld = done; assign sarld = gt & keep | gt & remove | gt & adstart & start; assign sh = ~done & keep | ~done & remove | adstart & start; endmodule

25. A/D Control Unit

26. // Title : A/D converter module adconv(clock, clear, adstart, gt, adflg, sar, adreg); input clock, clear, adstart, gt; output adflg; output [3:0] sar, adreg; wire adflg, msel, sarld, adld, sh, done; wire [3:0] sar, adreg; ADpath adc1(.clk(clock),.reset(clear),.sh(sh),.sarld(sarld),.adld(adld),.sar(sar),.ADR(adreg),.done(done)); ADctrl adc2(.Clk(clock),.Clear(clear),.gt(gt),.adstart(adstart),.done(done),.sarld(sarld),.sh(sh),.adld(adld),.adflg(adflg)); endmodule

28. Lab 9