1. 15-447 Computer ArchitectureFall 2008 © November 10, 2007 Nael Abu-Ghazaleh naelag@cmu.edu http://www.qatar.cmu.edu/~msakr/15447-f08 Lecture 23 Virtual Memory (2) CS 15-447: Computer Architecture

2. 15-447 Computer ArchitectureFall 2008 © 2 Last Lecture Virtual memory lets the programmer “see” a memory array larger than the DRAM available on a particular computer system. Virtual memory enables multiple programs to share the physical memory without: –Knowing other programs exist (transparency). –Worrying about one program modifying the data contents of another (protection).

3. 15-447 Computer ArchitectureFall 2008 © 3 Page table register 0x000020x082 0Disk address valid Physical page number Exception: page fault 1.Stop this process 2.Pick page to replace 3.Write back data 4.Get referenced page 5.Update page table 6.Reschedule process Page Table Components

4. 15-447 Computer ArchitectureFall 2008 © 4 Other VM Functions Page data location –Physical memory, disk, uninitialized data Access permissions –Read only pages for instructions Gathering access information –Identifying dirty pages by tracking stores –Identifying accesses to help determine LRU candidate

5. 15-447 Computer ArchitectureFall 2008 © 5 Page Replacement Strategies Page table indirection enables a fully associative mapping between virtual and physical pages. How do we implement LRU? –True LRU is expensive, but LRU is a heuristic anyway, so approximating LRU is fine –Reference bit on page, cleared occasionally by operating system. Then pick any “unreferenced” page to evict.

6. 15-447 Computer ArchitectureFall 2008 © 6 Two problems Size of page table – can be big –Do we have one page table per machine or one page table per process? Performance: –How many times do we access memory per instruction? –Can we afford to access a page table to do translation with every memory access?

7. 15-447 Computer ArchitectureFall 2008 © 7 Hierarchical Page Table Example Virtual SuperpageVirtual pagePage offset Virtual address 1 2 nd level page table valid super page table 1 page 1 Physical page number valid 2 nd level page table Physical page number Page offset Physical address Page table register 1 page

8. 15-447 Computer ArchitectureFall 2008 © 8 Problem 2: Performance We must access physical memory to access the page table to make the translation from a virtual address to a physical one Then we access physical memory again to get (or store) the data A load instruction performs at least 2 memory reads A store instruction performs at least 1 read and then a write.

9. 15-447 Computer ArchitectureFall 2008 © 9 Translation Lookaside Buffer We fix this performance problem by avoiding memory in the translation from virtual to physical pages. We buffer the common translations in a translation lookaside buffer (TLB)

10. 15-447 Computer ArchitectureFall 2008 © 10 TLB Virtual page vtagPhysical page Pg offset

11. 15-447 Computer ArchitectureFall 2008 © 11 Where is the TLB Lookup? We put the TLB lookup in the pipeline after the virtual address is calculated and before the memory reference is performed. –This may be before or during the data cache access. –Without a TLB we need to perform the translation during the memory stage of the pipeline.

12. 15-447 Computer ArchitectureFall 2008 © 12 Placing Caches in a VM System VM systems give us two different addresses: virtual and physical Which address should we use to access the data cache? –Virtual address (before VM translation) Faster access? More complex? –Physical address (after VM translations) Delayed access?

13. 15-447 Computer ArchitectureFall 2008 © 13 Physically-Addressed Caches Perform TLB lookup before cache tag comparison. –Use bits from physical address to index set –Use bits from physical address to compare tag Slower access? –Tag lookup takes place after the TLB lookup. Simplifies some VM management –When switching processes, TLB must be invalidated, but cache OK to stay as is.

14. 15-447 Computer ArchitectureFall 2008 © 14 Page offsetVirtual page Picture of Physical Caches Virtual address Set1 tag Set0 tag Set2 tag Tag cmp Tag cmp Cache tagPPN tagPPN tagPPN tagPPN Page offsetPPN tag index Block offset

15. 15-447 Computer ArchitectureFall 2008 © 15 Virtually-Addressed Caches Perform the TLB lookup at the same time as the cache tag compare. –Uses bits from the virtual address to index the cache set –Uses bits from the virtual address for tag match. Problems: –Aliasing: Two processes may refer to the same physical location with different virtual addresses. –When switching processes, TLB must be invalidated, and dirty cache blocks must be written back to memory.

16. 15-447 Computer ArchitectureFall 2008 © 16 Picture of Virtual Caches tagindex Block offset Virtual address Set1 tag Set0 tag Set2 tag Tag cmp Tag cmp TLB is accessed in parallel with cache lookup Physical address is used to access main memory in case of a cache miss.

17. 15-447 Computer ArchitectureFall 2008 © 17 OS Support for Virtual Memory It must be able to modify the page table register, update page table values, etc. –To enable the OS to do this, AND not the user program, we have different execution modes for a process – one which has executive (or supervisor or kernel level) permissions and one that has user level permissions.

18. 15-447 Computer ArchitectureFall 2008 © 18 Extended Example: Loading a Program into Memory text2 Istatic text1 Disk Pages2 entry TLB Memory Page Table 0 1 2 3 1000 1001 1002 1003 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs

19. 15-447 Computer ArchitectureFall 2008 © 19 Additional Information Page size = 4KB Page table entry size = 4B Page table register points to physical address 0000

20. 15-447 Computer ArchitectureFall 2008 © 20 Step 1: Read Executable Header and Initialize Page Table text2 Istatic text1 Disk Pages2 entry TLB reserved Memory Page Table D1000 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs ro

21. 15-447 Computer ArchitectureFall 2008 © 21 Step 2: Load PC from Header and Start Execution text2 Istatic text1 Disk Pages2 entry TLB reserved Memory Page Table D1000 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs ro MISS!

22. 15-447 Computer ArchitectureFall 2008 © 22 Fetching instr 0000 text2 Istatic text1 Disk Pages2 entry TLB reserved Memory Page Table D1000 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault ro

23. 15-447 Computer ArchitectureFall 2008 © 23 Fetching instr 0000 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Memory Page Table M1 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 ro 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault ro

24. 15-447 Computer ArchitectureFall 2008 © 24 Fetching instr 0000 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Memory Page Table M1 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 ro 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 ro

25. 15-447 Computer ArchitectureFall 2008 © 25 Fetching instr 0004 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Memory Page Table M1 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 ro 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 ro HIT!

26. 15-447 Computer ArchitectureFall 2008 © 26 Reference 7FFC text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Memory Page Table M1 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 ro 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 ro MISS!

27. 15-447 Computer ArchitectureFall 2008 © 27 Reference 7FFC text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Memory Page Table M1 D1001 D1002 no map 0 1 2 3 1000 1001 1002 1003 ro 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 No map page fault ro

28. 15-447 Computer ArchitectureFall 2008 © 28 Reference 7FFC text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Set to 0s Memory M27000 Page Table M1 D1001 D1002 no map M2 0 1 2 3 1000 1001 1002 1003 ro rw 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC ro

29. 15-447 Computer ArchitectureFall 2008 © 29 Fetching instr 0008 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Set to 0s Memory M27000 Page Table M1 D1001 D1002 no map M2 0 1 2 3 1000 1001 1002 1003 ro rw 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 ro HIT!

30. 15-447 Computer ArchitectureFall 2008 © 30 Reference 2134 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Set to 0s Memory M27000 Page Table M1 D1001 D1002 no map M2 0 1 2 3 1000 1001 1002 1003 ro rw 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 ro MISS!

31. 15-447 Computer ArchitectureFall 2008 © 31 Reference 2134 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Set to 0s Memory M27000 Page Table M1 D1001 D1002 no map M2 0 1 2 3 1000 1001 1002 1003 ro rw 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 Page fault ro

32. 15-447 Computer ArchitectureFall 2008 © 32 Reference 2134 text2 Istatic text1 Disk Pages M10000 2 entry TLB reserved text1 Set to 0s Istatic Memory M32000 Page Table M1 D1001 M3 no map M2 0 1 2 3 1000 1001 1002 1003 ro rw 0 1 2 3 4 5 6 7 References 0000 0004 7FFC 0008 2134 Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 Page fault 3134 ro

33. 15-447 Computer ArchitectureFall 2008 © 33 Multiple Processes Virtual cache support for multiple processes: –Flush the cache between each context switch. –Use processID (a unique number for each processes given by the operating system) as part of the tag

34. 15-447 Computer ArchitectureFall 2008 © 34 Multiple Processors Can run two programs at the same time –Each processor has its own cache. Why? May or may not share data –Sharing code is not a problem (read only) Example: shared libraries, DDLs –Sharing data (read/write) is a problem What if it is in one processors cache? –Solution: Snoopy caches