1. P09311 Interface for Multipurpose Driver/ Data Acquisition System

2. Team Adam Van Fleet (EE) –DAQ Hardware Development –FPGA/DAQ Hardware Interface Development –Project Leader David Howe (EE) –DAQ Interfacing & USB Hardware Development –FPGA/DAQ Hardware Interface Development Michael Doroski (CE) –DAQ Interface Development (software) –Custom FPGA logic Thomas (TJ) Antonoff (CE) –USB interface development (software) Andrew Weida (CE) –FPGA Bluetooth interface development (UART) –GUI Development and PC Serial Communication

3. Customer Needs Customer Need # ImportanceDescriptionComments/Status CN1HighInterfaces DAQ to FPGA CN2HighInterfaces FPGA to PC CN3HighUtilizes USB interface CN4ModerateUtilizes Bluetooth Wireless interface CN5LowUSB Transfer rate minimum of 1.5Mbits/s and 12Mbits/sDepends on bottleneck limitations. CN6LowBluetooth transfer rate minimum of 3Mbits/sDepends on bottleneck limitations. CN7Low100% message transfer percentage (no lost packets) CN8HighCapable of transferring numerical data CN9HighGUI - Connection settings available CN10HighGUI - Connection speed and status displayed CN11LowGUI - Displays GUI on Windows Operating System CN12HighGUI - Data Storage SystemAsk Lukowiak - Does it need to store or only stream? CN14LowInterchangeable FPGA'sDesign for 1, but needs to work for others. CN15LowC# programming languageChosen for portability, no restrictions on language.

4. Project Specifications Engr. Spec. # ImportanceSource Specification (description) Unit of Measure Marginal Value Ideal ValueComments/Status ES1MEDCN5 USB Transfer rate min of 1.5Mbits/s and max 12Mbits/sMb/s1.5/121.5-12 ES2MEDCN6Bluetooth Transfer rate min of 3Mbits/sMb/s33 ES3MEDCN8100% message transfer percentage (no lost packets)Packets0100% ES4LOWCN2Utilizes Ethernet InterfaceMb/sN/A TBD in MSD II ES5LOWCN2Utilizes Wireless USB InterfaceMb/sN/A TBD in MSD II ES6LOWCN10Ethernet Transfer Rate min:Mb/sN/A TBD in MSD II ES7LOWCN9USB Wireless Transfer Rate min 3Mbits/sMb/s33 ES8LOWCN11Option for Multiple Bluetooth Connections# of modules33 ES9LOWCN11Option for Multiple USB Connections# of modules33 ES10MEDCN2FPGA Programming LanguageLanguageVHDL Feat. #ImportanceSource FeatureDescription F1HIGHCN2Utilizes USB Interface F2HIGHCN2Utilizes Bluetooth Wireless Interface F3HIGHCN3Capable of transferring data collected from the DAQ F4HIGHCN4GUI-Connection settings available F5HIGHCN1GUI-Connection speed and status displayed F6MEDCN7Interchangeable FPGAs to Meet CN2:ES13 & ES14 F7HIGHCN4GUI-Displays GUI on Windows Operating System F8HIGHCN4GUI-Data Storage System F9LOWCN4 GUI Programming Language

5. Hardware-Level System Overview RS-232 USB Parani ESD210SK Bluetooth Dev. Kit Digilent Spartan-3 Board DLP-USB245M USB Adapter Windows-Based PC P08311 DAQ Board 32-pin (500 kbps xfer) ASIC or Robotics Input 12-pin (up to 1MB/s xfer)

6. Pin-Outs for Additional Hardware 7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 5 6 First 30 pins from connector A2 Second 2 pins from connector A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O RD I/O WR TXE RXF DLP-USB245M Pins 13-24 are connected to FPGA pins 7 through 18 of connector A1

7. Data Flow Chart

8. DAQ FPGA Dual-Input Buffer Custom Logic Dual- Output Buffer Dual-Input Buffer Dual- Output Buffer USB Data Routing Logic Dual- Output Buffer Dual-Input Buffer USB FIFO UART USB Cable Bluetooth Modules Rx Tx Rx Tx RS232 1.2 - 230 kbps Bluetooth Wireless Serial Top Level: USB & Bluetooth Architecture Design PC 500 kbps 8 Mbps

9. A/D Conversion on DAQ

10. D/A Conversion on DAQ

11. Data Path from DAQ to FPGA (Serial to Parallel Conversion)

12. Data Path from FPGA to DAQ (Parallel to Serial Conversion)

13. Custom Logic Diagram

14. Custom Logic FSM State Diagrams FSM_InFSM_Out

15. Dual Buffer Layout

16. USB Read State Diagram StateTitleSignalsDescription 1IdleRXF = 1, RD = 1, Write EN = 0, ACK = 0, Control = 1 RXF buffer is empty or filling (less than 1 byte in USB RXF buffer) 2SendingRXF = 0, RD = 0, Write EN = 1, ACK = 0, Control = 0 One byte of data sent in parallel to buffer on FPGA. 3ReloadRXF = 0, RD = 1, Write EN = 1, ACK = 1, Control = 1 Write acknowledge forces the USB buffer to load next byte into position for read. 4EmptyRXF = 1, RD = 1, Write EN = 0, ACK = 1, Control = 1 When USB RXF buffer empty, go back to idle state

17. USB Write State Diagram StateTitleSignalsDescription 1IDLEEN = 0, TXE = 0, WR = 1FPGA buffer doesn’t have enough information to send to USB yet or USB buffer is full and needs to wait for space to be made. 2WRITEEN = 1, TXE = 0, WR = 0FPGA is ready to write to USB. USB takes 1 bye in parallel from the FPGA buffer to the USB TXE buffer. 3RELOAD / DELAY EN = 1, TXE = 1, WR = 1Write from USB goes high to allow for storage of byte just written.

18. PinNameDirectionDescription 1CD«—Carrier Detect 2RXD«—Receive Data 3TXD—»Transmit Data 4DTR—» Data Terminal Ready 5GNDSystem Ground 6DSR«—Data Set Ready 7RTS—»Request to Send 8CTS«—Clear to Send 9RI«—Ring Indicator Hardware flow control is not supported on the connector. The port’s CD, DTR, and DSR signals connect together. Similarly, the port’s RTS and CTS signals connect together. The Parani-ESD has configurable hardware flow control. When hardware flow control is not being used, the Parani-ESD clears the buffer to secure room for the next data when the buffer becomes full. Loss of data may occur. As the transmission data becomes large, the possibility of data loss becomes greater. Spartan-3 Starter Board – RS232 Interface

19. SignalDescription CLKSystem Clock RSTAsynchronous active-high reset. Din[7:0]Eight-bits Data From Buffer LDLoad pulse to load Din in the Transmitter and start the transmission RxRS232 receive signal input. Is ’1’ when the line is idle. TxRS232 transmit signal output. Is ’1’ when the line is idle. Dout[7:0]Data received. RxRDYA ‘1’ pulse (one system clock cycle long) indicates that a character is received and is available at Dout. TxBusyIndicates that the UART is busy sending data. Will ignore any LD request. SDin[7:0] / SDout[7:0]Data received from RS-232 BuffDin[7:0] / BuffDout[7:0]Data From dual buffer, to be transmitted by UART WriteBuff / ReadBuffControl signal to write or read to/from Dual Buffer BuffFull / BuffEmptyIndicates if Buffers are Full or Empty. UART System

20. idle stop_tx load_tx_data Tx_data UART Transmit State Machine Put data in correct format: start+data bits tx_tick = 1 tx_bit_cnt = 1 -Shift out data bit by bit -Decrement tx_bit_cnt Stop_bit: When LD = ‘1’ Latch input data LD = ‘1’ Keep TxBusy asserted

21. UART Receive State Machine shift_rx stop_rx idle start_rx rx_ovf edge_rx Wait on Rx_d falling edge (start bit occurs) Wait on start bit: - Synchronize with rx_tick - Sample RX at mid-bit and verify the Start bit Sample Data: -shift rx into a register -increment bit counter Here during stop bit Latch data to output RX_RDY = ‘1’ rx_tick = 1 Framing error RxBitCnt = 8 rx_tick = 1 Rx_d = 0 Rx_d = 1 rx_tick = 1 Should be near Rx _d edge rx_tick = 1

22. Data Storage Format:,timestamp; GUIData Manager Control Signals Data Connection Info PC USB Cable PC Architecture Design (C#) Connection Handler Serial Cable Connection Media Connection Handler using System.IO.Ports: SerialPort Class

23. GUI Class Diagram

24. GUI Concept Design

25. Risk ItemLevelOwnerStatus and/or Contingency PlansDecision Date Transfer of knowledge from work of P08311 will be necessary for full system understanding LOWAdamMeet with Andrew Fitzgerald (P08311 Team Lead) to gather prior knowledge 10/3/08 Technological understanding of hardware / software to be used will be critical to success HIGHAll Team Members Personal research / professional help will be requiredOngoing Transition from embedded processor may pose problems LOWAll Team Members Will require knowledge of P08311’s shortcomings10/17/08 Possibility for data transmission bottlenecks at FPGA interfaces CRITAdam, Andrew, TJ, Dave Develop alternative method for data transmission (multiple devices in parallel, controlling the DAQ clock speed, memory storage of data, etc.) 10/17/08 No background in Bluetooth or USB; interface will require considerable time to produce MEDAdam, Andrew, TJ, Dave Extensive research of modes of data transfer will be requiredEnd of Quarter Shortcomings of P08311’s work (Compact flash memory, embedded PowerPC processor, etc.) will need to be evaluated MEDAll Team Members Research into previous data bottlenecks and possible solutions10/17/08 Interfacing FPGA to DAQ without any I/O expansion will pose a problem (Spartan-3 board) HIGHAdam, DaveResearch of FPGA’s containing enough I/O’s to handle all inputs/outputs from the DAQ board 10/17/08 Interfacing FPGA to Bluetooth / USB without any I/O expansion will pose a problem (Spartan-3 board) HIGHAdam, DaveResearch of FPGA’s containing enough I/O’s to handle all inputs/outputs from the DAQ board 10/17/08 VHDL knowledge (3 members have basic knowledge, 2 members have almost no knowledge) HIGHAll Team Members All team members will need to educate themselves in this area, as majority of software side of project revolves around VHDL End of Quarter Accurate monitoring of connection speed and status via GUI LOWMikeDecrease refresh rate to allow for better calculationEnd of Quarter Risk Assessment

26. Appendix Spartan-3 Board Reference Material http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Pro ducts&Nav2=Programmable DLP-USB245M USB Adapter http://www.dlpdesign.com/usb/usb245.shtml Parani ESD210SK Bluetooth Dev. Kit http://www.rfphone.com/files/ESD110.pdf