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1 DISE: A Programmable Macro Engine for Customizing Applications Marc Corliss, E Lewis, Amir Roth (U Penn), ISCA 2003 DISE (Dynamic Instruction Steam Editing)

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Presentation on theme: "1 DISE: A Programmable Macro Engine for Customizing Applications Marc Corliss, E Lewis, Amir Roth (U Penn), ISCA 2003 DISE (Dynamic Instruction Steam Editing)"— Presentation transcript:

1 1 DISE: A Programmable Macro Engine for Customizing Applications Marc Corliss, E Lewis, Amir Roth (U Penn), ISCA 2003 DISE (Dynamic Instruction Steam Editing) LBA Reading Group Presentation Shimin Chen

2 2 Overview Application customization functions (ACFs) E.g., safety-checking, debugging, code decompression (embedded processors), dynamic optimization … Why? new platforms  new requirements: power, safety … ACF implementation Binary rewriting (BR): + flexible functionality, – performance Hardware widget (HW): + little performance loss, – ACF specific Dynamic Instruction Stream Editing (DISE) Combo of HW and SW: a hardware widget that does rewriting + Rich functionality, + low cost

3 3 DISE Programmable instruction macro-expander Like a hardware “sed” (DISE = dynamic instruction sed) Executes rewrite rules (productions) on fetch stream Looks for instructions that match patterns… replaces them with parameterized sequences (repseq) Orthogonal to  ops  ops: finer-granularity, same functionality DISE: same granularity, different functionality I$executeDISE app app+ACF

4 4 Advantages of This Picture + Generality (wrt HW) Instruction-based ACFs That can modify (not just observe) application + Performance (wrt BR) Avoid costs of inserting ACF code into binary + Convenience (wrt both) Avoid pain of rewriting binary Avoid pain of implementing new widget + Non-subvertability (new) The last thing that can/will manipulate code, guaranteed I$executeDISE app app+ACF

5 5 Talk Outline Introduction Basic Capabilities Implementation Formulating ACFs Numbers Related work, Status, Future

6 6 What DISE Does Example customization functionality Compare upper store address bits to const, ERROR on mismatch DISE implementation Pattern store *, *(*) // store = match, * = don’t care Repseq srli T.RS,#26,R1 // template cmp R1,R2,R1 // T.* = instantiation directive bne R1, ERROR T.INSN store R4,8(R9) srli R9,#26,R1 cmp R1,R2,R1 bne R1,ERROR store R4,8(R9)

7 7 Pattern Matching and Parameterized Replacement Patterns consist of: opcode, opcode class, register name (e.g. stack pointer), immediate field or its sign (e.g. negative branch offset) ACF may use: literal, dedicted, T.RS, T.RT, T.RD

8 8 More DISE Capabilities (And Restrictions) – Restriction: peephole transformations only Capabilities Dedicated Registers Not accessible via application code Scratch storage (no need to scavenge) Inter-repseq communication (synthesize global behavior): persist across ACF sequences DISEPC Extend the PC to PC:DISEPC For an app instruction, it is PC:0 For an repseq instruction, DISEPC is offset from the start of repseq and PC is the triggering instruction’s PC Precise interrupt at PC:DISEPC Control-flow: change either PC or DISEPC but not both Jump to an app instruction; or jump inside the current repseq; but cannot jump into the middle of another reqseq

9 9 How DISE Does It Three components (well-understood, resemble  op) I$execute DISE Engine RT Replacement Table (RT): bigger RAM holds repseq specs Each entry is one instruction with repseqID and DISEPC IL Instantiation Logic (IL): executes directives to produce actual insns PT Pattern Table (PT): small associative table holds pattern specs Resolving ties: choose spec matching largest number of bits Logically: DISE then decode native decoder

10 10 How DISE Really Does It Physically: interleave DISE/decode implementations RISC: PT + decoded RT in parallel with native decoder CISC(+  ops): PT +  op RT in same physical structures

11 11 Talk Outline Introduction Basic Capabilities Implementation Formulating ACFs Numbers Related Work, Status, Future

12 12 Formulating ACFs Two kinds: transparent and aware (wrt application) Transparent: unmodified applications work without DISE DISE redefines “naturally-occurring” instructions Examples: fault isolation (just saw), profiling, etc. Aware: modified applications rely on DISE DISE converts “planted” codewords to runtime code Examples: decompression (see soon), dynamic optimization, etc. ACFs can be composed

13 13 Transparent ACF: Memory Fault Isolation [Wahbe+95]: multi-module safety in one address space How? Check upper address bits of loads, stores, ijumps Have seen, but to recap… Binary rewriting R: move T.RS, R3 srli T.RS,#26,R1 cmpeq R1,R2,R1 bne R1,ERROR store T.RD,T.IMM(R3) – Scavenge R1,R2,R3 – Retarget surrounding branches – move thwarts malicious jumps DISE R: srli T.RS,#26,DR1 cmpeq DR1,DR2,DR1 bne DR1,ERROR store T.RD,T.IMM(T.RS) + DISE registers DR1,DR2 + No branch retargeting

14 14 Aware ACF: Decoder Decompression [Lefurgy+97]: decoder + dictionary  compressed I$ How? Codewords = reserved opcode + dictionary index Uncompressed code add R2,R3,R2 load R4,8(R2)... add R1,R3,R1 load R4,8(R1) Hardware Widget D0: add R2,R3,R2 load R4,8(R2) D1: add R1,R3,R1 load R4,8(R1) Compressed code reserved #0... reserved #1 DISE: RT = dictionary Exploit parameterized replacement Compressed code reserved R2 #0... reserved R1 #0 Uncompressed code add R2,R3,R2 load R4,8(R2)... add R1,R3,R1 load R4,8(R1) + More efficient dictionary usage + Can compress branches R0: add T.RS,R3,T.RS load R4,8(T.RS)

15 15 Talk Outline Introduction Basic Capabilities Implementation Formulating ACFs Numbers Related Work, Status, Future

16 16 Experimental Setup Alpha ISA SimpleScalar-based timing simulator 4-way superscalar, 12-stage pipeline, 128 instruction window 32KB primary caches, 1MB L2 DISE configuration 32-entry PT (256 bytes), 512-entry RT (3KB) PT/RT miss handler: flush + 30 cycle stall on SPEC2K integer benchmarks Binary rewriting: perl script on.S files

17 17 Fault Isolation: DISE vs. Binary Rewriting Point: DISE performs better than corresponding BR Metric: exec. time norm. to 4-wide, 32KB I$, unmodified Exp2: increase proc. width Dynamic cost disappears Static cost dominates + DISE adds no footprint Exp1: increase I$ size Footprint cost disappears Bandwidth cost dominates + DISE adds fewer instructions + I$ size effectively decreasing gcc twolf parser

18 18 Decompression: DISE vs. Hardware Widget Point: DISE more flexible (?) than corresponding HW Metric: code size norm. to uncompressed Also in paper: RT sensitivity, composed ACF performance More about DISE decompression [Corliss+, LCTES03], Fri. 2:30 Exp1: parameterization + Parameterization (DISE) helps + DISE is general-purpose gccparsertwolf

19 19 To Summarize DISE: a HW/SW solution for customizing applications Like a hardware SED or AWK + More general than hardware + Faster than software + Has some other nice properties (e.g., non-subvertability) Near future: apps to exploit “other nice properties” Non-subvertability  security applications Painless code modification  runtime optimization Your questions

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