1. Overview Finite State Machines - Sequential circuits with inputs and outputs State Diagrams - An abstraction tool to visualize and analyze sequential circuits Internal Memory - Random Access Memory (RAM) - Volatile – values lost on power loss - Static RAM (SRAM) - Dynamic RAM (DRAM) - Read Only Memory (ROM)

2. Combinational vs. Sequential Logic There are two types of “combination” locks 4184 30 15 5 1020 25 Combinational: Success depends only on the values, not the order in which they are set. Sequential: Success depends on the sequence of values (e.g, R-13, L-22, R-3).

3. Combinational vs. Sequential Circuits Combinational Circuit –always gives the same output for a given set of inputs example: adder always generates sum and carry, regardless of previous inputs Sequential Circuit –has memory - “stores” information, –output depends on stored information (state) plus input so a given input might produce different outputs, depending on the stored information

4. State Machine A type of sequential circuit –Combines combinational logic with storage –“Remembers” state, and changes output (and state) based on inputs and current state State Machine Combinational Logic Circuit Storage Elements InputsOutputs

5. State The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. Examples: –The state of a basketball game can be represented by the scoreboard. (Number of points, time remaining, possession, etc.) –The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board.

6. State of Sequential Lock Our lock example has four different states, labelled A-D: A: The lock is not open, and no relevant operations have been performed. B:The lock is not open, and the user has completed the R-13 operation. C:The lock is not open, and the user has completed R-13, followed by L-22. D:The lock is open.

7. Finite State Machine A description of a system with the following components: 1.A finite number of states 2.A finite number of external inputs 3.A finite number of external outputs 4.An explicit specification of all state transitions 5.An explicit specification of what determines each external output value Often described by a state diagram. - The set of all possible states. - Inputs that trigger state transitions. - Outputs associated with each state (or with each transition).

8. State Diagram Shows states (e.g. A), actions (e.g. B) that cause a transition between states, and the outputs. Open Locked

9. The Clock Frequently, a clock circuit triggers transition from one state to the next. At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external inputs (Synchronous). –Not always required. In lock example, the input itself triggers a transition (Asynchronous). “1” “0” time  One Cycle

10. Implementing a Finite State Machine Combinational logic –Determine outputs at each state. –Determine next state. Storage elements –Maintain state representation. State Machine Combinational Logic Circuit Storage Elements InputsOutputs Clock

11. Storage Each D flipflop stores one state bit. The number of storage elements (flipflops) needed is determined by the number of states (and the representation of each state). Examples: –Sequential lock Four states – two bits –Basketball scoreboard 7 bits for each score digit, 5 bits for minutes, 6 bits for seconds,1 bit for possession arrow, 1 bit for half, …

12. Complete Example – Traffic Sign Design a “blinking” traffic sign which exhibits this behavior: State 1) No lights on  State 2) 1 & 2 on  State 3) 1, 2, 3, & 4 on  State 4) 1, 2, 3, 4, & 5 on  State 1) No lights on . ( - Repeat as long as operate switch is turned on. - The system is in state 1 when the operate switch is off) DANGER MOVE RIGHT 1 2 3 4 5

13. Traffic Sign State Diagram State bit S 1 State bit S 0 Switch on Switch off Outputs State Transitions occur on each clock cycle.

14. Traffic Sign Truth Tables Outputs (depend only on state: S 1 S 0 ) S1S1 S0S0 ZYX 00000 01100 10110 11111 Lights 1 and 2 Lights 3 and 4 Light 5 Next State: S 1 ’ S 0 ’ (depend on state and input) InS1S1 S0S0 S1S1 S0S0 0XX00 10001 10110 11011 11100 Switch Whenever In=0, next state is 00.

15. Traffic Sign Combinational Logic Edge Triggered D flipflops

16. Another Example of a State Machine Digital Computer “States”: 1.Fetch Instruction 1.Fetch Operand(s) 1.Execute Operation 1.Store Result 1.Check for Interrupt 2.Go to 1.

17. Computer Memory

18. Computer Memory Hierarchy

19. Main Memory Address Space –The number of uniquely addressable memory locations Addressability –The number of bits stored at an addressable location Unit of Transfer –The number of bits transferred in a memory read or write {could be the “addressability” or a multiple of it, i.e. the addressability could be –an 8 bit byte, or –a 32 bit word (4 bytes) }

20. Basic Types of Memory Two basic kinds of RAM (Random Access Memory) Static RAM (SRAM) –fast, maintains data as long as power applied Dynamic RAM (DRAM) –slower but denser, bit storage decays – must be periodically refreshed. Refreshing interferes with regularity of execution of instruction stream. Also, non-volatile memories: ROM, PROM, flash, …

21. Memory Map 00 00000000 01 01010101 02 11001010 03 00011001.. FF 11001100 What is the Address Space of this memory? What is the Word Length of this memory? What is the Unit of Transfer of this memory?

22. Memory Organization What would a 1 word by 1 bit memory look like? –How could data be stored in it? –How could data be read from it? What would a 1 word by 2 bit memory look like? –How could data be stored in it ? –How could data be read from it ? What would a 2 word by 1 bit memory look like? –How could data be stored in it ? –How could data be read from it ?

23. 2 2 x 3 Memory Organization address decoder word selectword WE address write enable input bits output bits

24. 2 2 x 3 Memory – 1 Decoder, 3 Multiplexors

25. 2 2 x 3 Memory – Read of Word at Address 11

26. Memory Design – 1K x 4 A[09:00]   D[03:00] Addr Block Select 

27. Memory Design – 1K x 8 A[09:00]    D[07:04] A[09:00]    D[03:00] Addr Block Select => D[07:04] D[03:00]

28. Memory Design - 2k x 8 D[07:04] D[03:00] Block 01 Block 00

29. Memory Design - 4k x 8 D[07:04] D[03:00] Block 11 Block 10 Block 01 Block 00