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Didier Ferrère, Geneva University Como, October 2001 1 The Construction Status of the ATLAS Silicon Microstrip Tracker D. Ferrère on behalf of the SCT.

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Presentation on theme: "Didier Ferrère, Geneva University Como, October 2001 1 The Construction Status of the ATLAS Silicon Microstrip Tracker D. Ferrère on behalf of the SCT."— Presentation transcript:

1 Didier Ferrère, Geneva University Como, October 2001 1 The Construction Status of the ATLAS Silicon Microstrip Tracker D. Ferrère on behalf of the SCT collaboration DPNC, University of Geneva General Description Silicon Detectors Electronics Electrical Tests Module Assembly Summary & Status

2 Didier Ferrère, Geneva University Como, October 2001 2 Atlas at LHC Atlas LHC will provide protons and ions collisions A designed luminosity of 10 34 cm -2 s -1 p-p collision with 14 TeV in the center of mass

3 Didier Ferrère, Geneva University Como, October 2001 3 The Atlas Detector

4 Didier Ferrère, Geneva University Como, October 2001 4 Physics Motivations Simulated Event in the Inner Detector Higgs in SM and in MSSM Supersymmetric Particles B physics (CP violation,...) Exotic physics Requires a good tracking performance:  Secondary vertices  Impact parameters resolution  Track isolation  Measurement of high momentum particles

5 Didier Ferrère, Geneva University Como, October 2001 5 SCT Environment  23 overlapping interactions every bunch crossing (at the full Luminosity)  A bunch-bunch crossing every 25ns (40MHz)  Maximum equivalent 1 MeV neutron fluence after 10 years is ~ 2.10 14 n/cm 2  Operating temperature on silicon detectors is -7 o C to contain the reverse annealing and the leakage current  Maintenance will likely require yearly warm-up of 2 days at 20 o C and 2 weeks at 17 o C  Material < 0.4 X 0 at the outer SCT envelope  Operation in a 2 Tesla solenoid field

6 Didier Ferrère, Geneva University Como, October 2001 6 SCT in the Inner Detector SCT: 4 Barrels + 2x9 wheels 4 different module types in the wheels  < 2.5

7 Didier Ferrère, Geneva University Como, October 2001 7 The SCT Semiconductor Tracker 4 barrels 9 wheels 5.6 m 1.04 m 1.53 m 4088 Modules ~ 61 m 2 of silicon 15,392 silicon wafers ~ 6.3 million of readout channels Barrel diameters: B3: 568 mm B4: 710 mm B5: 854 mm B6: 996 mm

8 Didier Ferrère, Geneva University Como, October 2001 8 The SCT module types Barrel 2112 Barrel modules 936 Outer Forward Modules 640 Middle Forward Modules (incl. 80 Short Middle) 400 Inner Forward Modules

9 Didier Ferrère, Geneva University Como, October 2001 9 Module Pictures A Barrel Module 2 daisy chained detectors / side The Kapton hybrid is bridged over the detectors The cooling pipe is on the connector side An Outer Forward Module 2 daisy chained detectors / side The Kapton hybrid is at the far end The cooling area is common with the mounting blocks

10 Didier Ferrère, Geneva University Como, October 2001 10 Silicon Detector Pictures Scratch pads for identification – Corresponds to DB serial number Barrel Pitch : 80  m Forward Pitch: W31 and W32: 161.5  rad W12, W21 & W22: 207  rad 1 Barrel detector type 5 Forward detector types: W12: Inner Module W21 & W22: Middle Module W31 & W32: Outer Module Single sided p-in-n detectors 285  m thick Size ~ 6x6 cm 2 768 strips

11 Didier Ferrère, Geneva University Como, October 2001 11 Silicon Detector Status Delivery status of Hamamatsu detectors in Geneva University The detectors passed the Production Readiness Review in August 2000. The production delivery started this year. ManufacturersHamamatsu (Japan) CiS (Germany) Sintef* (Norway) Contribution79%17%4% Sensor typesAllWedgesBarrels * On going qualification The detector purchases is distributed as followed:

12 Didier Ferrère, Geneva University Como, October 2001 12 Silicon Detector – Some Specifications  Total leakage current at 20 o C: <  A@150V and <2  A@350V  Leakage current stability: to increase by not more than  A @150V in dry air over 24 hours  Depletion Voltage < 150V  R bias = 1.25 +/- 0.75  (Poly-silicon or implanted technology)  C coupling >= 20 pF/cm @ 1kHz  C interstrip < 1.1pF/cm @ 100kHz @ 150V bias  R interstrip >2x R bias at operating voltage  Strip metal resistance <1  /cm  Strip quality: a mean of >99% good readout strips per delivery batch. Not less that 98% /detector  Total leakage current <250  A up to 450V @ -18 o C  Leakage Current stability:to vary by no more than 3% in 24 hours at 350V at -10 o C  Strip defects: Number of strip defects (dielectric & metal) within pre-irradiation acceptance level  Charge collection: Maximum operating voltage for >90% of maximum achievable charge : 350V Pre-Irradiation Post-Irradiation

13 Didier Ferrère, Geneva University Como, October 2001 13 Silicon Detector Quality Control Example of W31 normalized current @ 20 o C Quality Control consists of systematic checks for Visual Inspection and IV scan & sub-sample tests (10% of the detectors): Depletion voltage, full strip test, metal strip resistance and Interstrip capacitance Up to now only few rejections has been made based on visual defects and extra currents. nA

14 Didier Ferrère, Geneva University Como, October 2001 14 Silicon Detector Quality Control 0.082 % of detective strips out of 172 detectors 0.044 % of detective strips out of 170 detectors The defective strips are identified by Hamamatsu and the QC at the Institutes. The full strip test allows to identify all possible defects like: Open, Short, bias resistor break, pin hole, oxide punch through, implant break. The detectors are slightly biased during the measurement and up to 100V DC is put on the strips. LCR meter allows to measure coupling capacitance and the relative bias resistor. Hamamatsu series production delivered in Geneva

15 Didier Ferrère, Geneva University Como, October 2001 15 Silicon Detector – Irradiation The detectors are irradiated using 24 GeV protons at CERN PS. All strips are grounded and the backplane is biased to 100V during the irradiation. Typical annealing is done at the minimum of the beneficial and reverse annealing. AA V

16 Didier Ferrère, Geneva University Como, October 2001 16 Silicon Detector – Charge Collection after Irradiation Barrel W31 W32 350V The detectors were annealed 7 days at 25 o C after an irradiation of 3x10 14 p/cm 2 The readout was made with SCT 128A chips (DMILL technology). A Ru 106 source was used for the injected charge. The Signal to noise ratio is for a strip length of ~6 cm The measurement was taken at –18 o C A S/N plateau around 17:1 is reached above 350V for all the Hamamatsu detectors Similar results are obtained for the other detector purchases D. Robinson

17 Didier Ferrère, Geneva University Como, October 2001 17 The Front End Electronics Binary ABCD chips are based on DMILL BiCMOS technology Noise with detectors (12 cm strips): < 1500 e- Efficiency: 99% Occupancy due to Noise : 5x10 -4 Double pulse resolution: 50ns for 3.5fC following 3.5 fC signal Shaping time ~ 20 ns Pipeline Length: 3.2  s (128 locations) Functionality temperature range: -15 to 30 o C Power dissipation: < 3.8 mW/channel Specified total radiation dose: 2x10 14 n/cm 2 10 Mrad

18 Didier Ferrère, Geneva University Como, October 2001 18 The Front End Electronics ABCD 3T – Trimming function The readout chips passed the PRR in July 2001. Pre-series have started with 35 wafers already delivered. In November 200 wafers are expected. The measured yield on the pre-series is spread from 10 to 50 % and the expected yield in average is ~26%. ATMEL think they can improve it! The wafer screening for the Quality Control will be done at 3 places: CERN, RAL and SCIPP. Yield consideration based on: All analog and digital functionalities are OK (tested with threshold, bias and frequency scan) No Icc or Idd problem No bad channels Current testing time ~9 hours/wafer Will be decrease during prod by a factor 2

19 Didier Ferrère, Geneva University Como, October 2001 19 The Module Test Set-up Tests on modules: Measured gain curve (with internal calibration signal) Hit occupancy versus comparator threshold without signal (“Noise Occupancy”) Determination of ENC (from response curve and Noise Occupancy) Pulse shape through variation of calibration pulse delay Power consumption at different settings Various digital function checks (pipeline & data transfer) The SCT DAQ (software and hardware) readout test set-up is the same in all the laboratories.

20 Didier Ferrère, Geneva University Como, October 2001 20 Signal and ENC determination “S-curves”: Measure hit occupancy as a function of the threshold Fit error function to occupancy “S-curve” Determines mean signal & rms

21 Didier Ferrère, Geneva University Como, October 2001 21 Module Performances 5x10 -4 Pre-irradition ENC noise: 1400-1500e- ENC noise: 1400-1500e- NO @1fC: 1-2 x 10 -5 NO @1fC: 1-2 x 10 -5 Post-irradition ENC noise: 1900e- ENC noise: 1900e- NO @1fC: 2-3 x 10 -4 * NO @1fC: 2-3 x 10 -4 * * Acceptance criteria : 5x10 -4

22 Didier Ferrère, Geneva University Como, October 2001 22 KEK Test Beam – Median Charge Preliminary results from N. Unno Barrel and End-cap modules are functioning well and are very similar A small difference between barrel and end- cap modules is observed and could be due to: Larger effective pitch for the forward and less charge sharing. (V)

23 Didier Ferrère, Geneva University Como, October 2001 23 KEK Test Beam – Efficiency and Noise Occupancy Preliminary results from N. Unno Specs

24 Didier Ferrère, Geneva University Como, October 2001 24 Test Beam Results – Spatial Resolution Gives spatial resolution in X/Y  (X) = 20  m  (X) = 20  m  (Y) = 750  m  (Y) = 750  m Spatial resolution in strip coodinate (+/- 20mrad stereo angle)  23  m  compatible with digital resolution for 80  m pitch

25 Didier Ferrère, Geneva University Como, October 2001 25 Multiple Modules in the System Test  Determine performance of individual modules  Measure noise and “inter-module” effects  Optimize grounding and shielding in realistic setup

26 Didier Ferrère, Geneva University Como, October 2001 26 Noise Performance in the System Test Tests on multi-modules barrel setup

27 Didier Ferrère, Geneva University Como, October 2001 27 Noise Comparison System Test versus Single Module Test ENC System Test ENC Individual Module ENC Noise Occupancy

28 Didier Ferrère, Geneva University Como, October 2001 28 Module Assembly Parallel module production will take place Barrel: KEK, RAL, LBL, Oslo – Starting at the end of this year Forward: Freiburg, Geneva, Melbourne, Nikhef, MPI, UK-North, Valencia Aligned forward detector pairs onto transfer plates Barrel alignment system

29 Didier Ferrère, Geneva University Como, October 2001 29 Module Mechanical Tolerances SCT Philosophy: SCT Philosophy: Build modules to a sufficiently high tolerance that alignment corrections “within the module” are not needed for track reconstruction Physics requirement: Physics requirement: Alignment accuracy rms (in micron) Direction (cyl. Coord.) BarrelForward R10050  12 z50200 Internal module build tolerances: Internal module build tolerances: Alignment tolerance (in micron)BarrelForward XY wafer to wafer plane in 1 plane 44 XY back to front plane 88 XY relative to mounting holes 3020 Z surface of silicon detectors 40100

30 Didier Ferrère, Geneva University Como, October 2001 30 Engineering Forward disc sector Middle cooling circuits, cooling blocks and low mass tapes Barrel sector close-up view of brackets, pipes, modules… Barrel support structure is under construction Forward support structure is ready for FDR

31 Didier Ferrère, Geneva University Como, October 2001 31 Summary and Status  Detectors The series production started beginning of 2001 and is well on the way ~ 36% of the detectors are delivered and the quality is very good  Chips ABCD3T passed production readiness review and first lot of production wafers are expected soon  Modules Barrel modules passed FDR and will start production at the end of the year Forward modules require 1 more round of hybrid production before going to FDR  Engineering, Off-detector Components, power distribution A series of FDRs started in spring First parts are/will be soon order for production

32 Didier Ferrère, Geneva University Como, October 2001 32 Appendix - Typical Power Consumption Before IrradiationAfter Irradiation Idd (mA)550750 Vdd (V)4.04 Icc (mA)950560 Vcc (V)3.5 Power (W)5.25 ICC  after irradiation due to the optimization of the FE setting: before irr: Ipre = 220  A and Ishap = 30  A after irr: Ipre = 150  A and Ishap = 24  A Module current and power

33 Didier Ferrère, Geneva University Como, October 2001 33 Appendix – Prototype Components of the Forward Modules Spine Kapton Hybrid

34 Didier Ferrère, Geneva University Como, October 2001 34 Appendix – Optical Links Opto-packages on the dog-leg (Barrel) Forward Opto-plug-in: PIN receiver (Clock & Control BPM) & 2 VCSEL lasers for data links

35 Didier Ferrère, Geneva University Como, October 2001 35 Appendix – Forward Electrical Performances From G.Moorhead

36 Didier Ferrère, Geneva University Como, October 2001 36 Appendix – Forward Electrical Performances From G.Moorhead

37 Didier Ferrère, Geneva University Como, October 2001 37 Appendix – Thermal Simulation Requirement:  Requirement: Prevent Thermal Runaway  Facts of life:  Leakage current (4 detectors of the module) after 10 years in the LHC reaches ~2mA @ 500V @ -10  C (spec: <1. 0mA @450V @- 18  C)  Increased ASIC power estimates: now 6.8W per module  ASICs are close to detector and module designs are optimized to limit heat transfer to detectors.  Some thermal design features:  Baseboard or spine are made of TPG (Thermo Pyrolitic Graphite). Conductivity: 1700 W/ m/ K along length  Improved hybrid substrate (metallised CF or CC) reduces hybrid & ASIC temperatures, reducing convection (~ 0.5W with CF)  Evaporative C3F8 cooling - extensive system prototyping has been done. It looks promising using -20  C at the cooling block

38 Didier Ferrère, Geneva University Como, October 2001 38 Appendix – Thermal Simulation

39 Didier Ferrère, Geneva University Como, October 2001 39 Module Power Consumption After annealing (10 days continuous warm operation) observed on some modules increase of Idd current (up to x2 normal current) but still within specs for current and total module power (6.8W/module) on effected module current comes from all chips uniformly under investigation... @ 40MHz


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