1. Timing-Based Communication Refinement for CFSMs Presenters:Heloise Hse, Irene Po Mentors:Jonathan Martin, Marco Sgroi Professor:Alberto Sangiovanni-Vincentelli EE249 Course Project

2. Outline Problem descriptions Rendezvous based communication Buffer sizing Mixed HW/SW implementation with CPU contention Unresolved Issues Conclusion

3. Problem Descriptions Currently, CFSM networks in Polis use one- place buffer Non-blocking write If sender CFSM module sends faster than receiver can receive, events may be overwritten / lost

4. Rendezvous Based Communication Start with a rendezvous based specification –safe: events do not get lost –inefficient: senders have to wait until receivers are ready before sending more data Relax to bounded buffers wherever possible –use minimal buffer sizes –maintain lossless communication –preserve input-output behavior

5. Overview CFSM1CFSM2 CFSM3CFSM4 FSM3FSM4 FSM1FSM2... CFSM1CFSM2 CFSM3CFSM4...

6. Sizing Buffers Translate each CFSM module into an FSM using translator in Polis If state transition times are different, normalize the transition time by adding intermediate states AE BCD 10 20 15 10 20 55 AE B C D

7. Sizing Buffers Model each buffer as a FSM Compute the set of reachable states of the network from the transition relations using implicit state enumeration techniques R 0 =  R k+1 = R 0 V  (x,i)[R k  T(x,i,y)] R * = R k if R k+1 = R k “Sizing and Verification of Communication Buffers for Communicating Processes” by Tilman Kolks, Bill Lin, and Hugo de Man

8. Sizing Buffers Derive the set of reachable states for each communication buffer Determine the minimum buffer size from the reachable states of the buffer

9. Clock Handling Define a global “clock” (G c ) with frequency equal to the least common multiple of all frequencies f i (f i = clock frequency of FSM F i ) A FSM makes a transition only when it is active original transition (i, s) -> s’ replace by (i  active i, s) -> s’ (i  ¬active i, s)->s

10. Buffer Modeling Model buffers as counters (FSMs) –start with an estimated size for each buffer –increment buffer on write, decrement on read Initial buffer offset = 0 next state function: adder/subtracter add an output function to the buffer B i – i over = 1, iff an overflow condition occurs –expand the counters dynamically during state traversal when necessary

11. Reachable Buffer States Build transition relations for every FSM F i and buffer B k Build the transition relation (T C ) of the product machine over variables of the network Obtain the reachable state set from T C Expand the counters (buffers) dynamically during the state space traversal by adding an additional state variable if an overflow occurs

12. Minimum Buffer Size Derive the set of all reachable buffers states by existentially quantifying over all non-buffer state variables Derive the set of reachable states for a particular buffer by existentially quantifying (abstracting) out the other buffer states Determine the minimum buffer size from the largest value of the counter state

13. Mixed HW/SW Implementation with CPU Contention If several processes are sharing a CPU, there may be contention due to resource sharing Therefore we need to modify the buffer sizes to accommodate this case Sender Receiver

14. CPU Contention Assume the CFSM network is a DAG and there are no feedback signals To obtain safe minimum buffer size, assume –all the modules before and including the sender send at the fastest rate possible (i.e. get CPU right when it wants to execute) –receiver receives at the slowest rate (i.e. at end of queue every time it wants to execute) Size buffer one at a time HW/SW SW with CPU contection...

15. CPU Contention Build the reachable states table for processes that are sharing the same CPU Assume scheduler is FIFO For each state in an FSM –look at the possible states that other FSMs can be in, and put those processes in the front of the queue –Compute worst case waiting time P1 P2 P3 S1 S2S3 S1 S2 S3’ S1...

16. CPU Contention Compute worst case execution time (original execution time + worst case waiting time) and update the transition times in the original “FSM” For each “FSM”, again normalize the transition time by adding intermediate states Apply the buffer sizing algorithm on the normalized FSM’s

17. CPU Contention AE BCD 20 40 30 20 40 10 AE B C D

18. Issues: Abstraction State explosion problem during implicit state enumeration One solution: abstracting away non-buffer variables during state traversal – may lose relevant information for buffer sizing when environment is control-dominated in which events depend on both time and value –need to abstract away variables in a smart way

19. Issues: Environment Modeling In original buffer sizing algorithm, no assumption is made about the environment Approach is very conservative and buffers may be oversized Hard to model the environment Possible solution: given all properties of the environment or test vectors of all possible input patterns, model the environment as an FSM, and then apply the algorithm in the paper

20. Conclusions We presented an algorithm to find minimum- sized buffers between CFSM modules while maintaining lossless communication The case of CPU contention has been considered