1. Lecture 2 Introduction to Computer Architecture Topics Representations of Data Computer Architecture C Programming Unsigned Integers Signed magnitude Two’s complement January 12, 2011 CSCE 212 Computer Architecture

2. – 2 – CSCE 212H Spring 2011 Course Pragmatics Syllabus Instructor: Amber Mckenzie Slides from Publisher

3. – 3 – CSCE 212H Spring 2011 What is Computer Architecture? the attributes of a [computing] system as seen by the programmer…, as distinct from …the physical implementation. – Amdahl, Blaaw, and Brooks, 1964 Computer Architecture is the attributes of a [computing] system as seen by the programmer…, as distinct from …the physical implementation. – Amdahl, Blaaw, and Brooks, 1964 The term computer architecture was first used in 1964 the designers of the IBM System/360. The IBM/360 was a family of computers all with the same architecture, but with a variety of organizations(implementations).

4. – 4 – CSCE 212H Spring 2011 Instruction Set Architecture

5. – 5 – CSCE 212H Spring 2011 Register- Type (R-type) MIPS Instructions R-type Instruction format Encoding Add r2, r4, r3 // R2  R4 + R3 Opcode for Add ? rsrtrd

6. – 6 – CSCE 212H Spring 2011 MIPS Microarchitecture

7. – 7 – CSCE 212H Spring 2011 Instruction Set Architecture Instruction Set Architecture: 1. abtraction that hides the low-level details of a processor from the user 2. the interface between the hardware and software 3. everything you need to know to “use” the processor: instruction set instruction representations addressing modes etc… “Families” of processors are defined by their ISA: Sun Sparc Intel IA-32 MIPS IBM 360 Motorola/IBM PowerPC

8. – 8 – CSCE 212H Spring 2011 ISAs Today

9. – 9 – CSCE 212H Spring 2011 Processor Classes

10. – 10 – CSCE 212H Spring 2011 MIPS ISA 100 million MIPS processors manufactured in 2002 MIPS processors used in: Products from ATI, Broadcom, NEC, Texas Instruments, Toshiba SGI workstations Series2 TiVo Windows CE devices Cisco/Linksys routers Nintendo 64 Sony Playstation 1, PS2 (Emotion), PSP Cable boxes Competes against XScale/ARM for cell phones John L. Hennessy (Stanford, 1981) 1984: MIPS Computer Systems R2000 (1985), R3000 (1988), R4000 (64-bit, 1991) SGI acquisition (1992) => MIPS Technologies Transition to licensed IP: MIPS32 and MIPS64 (1999) “Heavyweight” embedded processor

11. – 11 – CSCE 212H Spring 2011 Lecture Outline Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

12. – 12 – CSCE 212H Spring 2011 MIPS Microarchitecture

13. – 13 – CSCE 212H Spring 2011 RISC vs. CISC Design “philosophies” for ISAs: RISC vs. CISC CISC = Complex Instruction Set Computer RISC = Reduced Instruction Set ComputerTradeoff: Execution time = instructions per program * cycles per instruction * seconds per cycle Problems with CISC: Compilers Off-chip memory references Complex control, unbalanced instruction set made parallelizing difficult MIPS is the first implementation of a RISC architecture

14. – 14 – CSCE 212H Spring 2011 RISC vs. CISC MIPS R2000 ISA Designed for use with high-level programming languages Easy for compilers Example: mapping IA32 instruction CRC32 (accumulate CRC32 value) Balance amount of work per instruction (pipelining) Load-store machine Force user to minimize off-chip accesses Fixed instruction width (32-bits), small set of uniform instruction encodings Reduce implementation complexity

15. – 15 – CSCE 212H Spring 2011 Lecture Outline Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

16. – 16 – CSCE 212H Spring 2011 MIPS Instruction Types MIPS instructions fall into 5 classes: Arithmetic/logical/shift/comparison Control instructions (branch and jump) Load/store Other (exception, register movement to/from GP registers, etc.) Three instruction encoding formats: R-type (6-bit opcode, 5-bit rs, 5-bit rt, 5-bit rd, 5-bit shamt, 6-bit function code) I-type (6-bit opcode, 5-bit rs, 5-bit rt, 16-bit immediate) J-type (6-bit opcode, 26-bit pseudo-direct address)

17. – 17 – CSCE 212H Spring 2011 Partial MIPS Instruction Set (see Appendix. A) Arithmetic R-type:add, addu, sub, subu Arithmetic I-type:addi, addiu Logical R-type:and, or, nor, xor Logical I-type:andi, ori, xori Compare R-type:slt, sltu Compare I-type:slti, sltiu Shift R-type:sll, sllv, srl, srlv, sra, srav Load/Store I-type:lui, lw, lh, lhu, lb, lbu, sw, sh, sb Branch I-type: beq, bne, bgez, bgezal, bgtz, blez, blezal, bltz Jump J-type:j, jal Jump R-type:jr, jalr OS support:syscall Multiply/divide:mult, multu, div, divu result held in 2 special registers (hi,lo) Floating-point instructions

18. – 18 – CSCE 212H Spring 2011 MIPS Registers 32 x 32-bit general purpose integer registers Some have special purposes These are the only registers the programmer can directly use $0 => constant 0 $1 => $at (reserved for assembler) $2,$3 => $v0,$v1 (expression evaluation and results of a function) $4-$7 => $a0-$a3 (arguments 1-4) $8-$15 => $t0-$t7 (temporary values) »Used when evaluating expressions that contain more than two operands (partial solutions) »Not preserved across function calls $16-$23 => $s0->$s7 (for local variables, preserved across function calls) $24, $25 => $t8, $t9 (more temps) $26,$27 => $k0, $k1 (reserved for OS kernel) $28 => $gp (pointer to global area) $29 => $sp (stack pointer) $30 => $fp (frame pointer) $31 => $ra (return address, for branch-and-links) Program counter (PC) contains address of next instruction to be executed

19. – 19 – CSCE 212H Spring 2011 Design Considerations Most arithmetic instructions have 3 operands simplifies the hardware Limits the number of datapaths on the processor Limiting to 32 registers speeds up register access time For memories, smaller is faster Influences clock cycle time

20. – 20 – CSCE 212H Spring 2011 Arithmetic Arithmetic (R-type) instructions add a,b,c  a = b + c sub a,b,c  a = b - c C code: f = (g + h) – (i + j)to… add t0,g,h add t1,i,j sub f,t0,t1 t0, t1, f, g, h, i, j must be registers

21. – 21 – CSCE 212H Spring 2011 Registers f, g, h, i, j in $s0, $s1, $s2, $s3, $s4 To… add $t0,$s1,$s2 add $t1,$s3,$s4 sub $s0,$t0,$t1 Similar instructions: addu, subu and, or, nor, xor slt, sltu

22. – 22 – CSCE 212H Spring 2011 Encoding R-type Instructions ADD $2, $3, $4 R-type A/L/S/C instruction Opcode is 0’s, rd=2, rs=3, rt=4, func=100000 000000 00011 00100 00010 00000 100000 00641020

23. – 23 – CSCE 212H Spring 2011 Immediate Instructions Second operand is a 16-bit immediate Signed (-32,768 to 32,767) or unsigned (0 to 65,535) Encoded with I-type addi $s0, $t0, -4 Similar I-type instructions: addiu andi, ori, xori lui

24. – 24 – CSCE 212H Spring 2011 Encoding I-Type Arithmetic/Logical/Compare ADDI $2, $3, 12 I-type A/L/S/C instruction Opcode is 001000, rs=3, rt=2, imm=12 001000 00011 00010 0000000000001100

25. – 25 – CSCE 212H Spring 2011 Load Upper Immediate Need more than 16 bits? Example: Initialize register $t0 with 12345678 16 lui $t0, 1234 addi $t1, $0, 5678 or $t0, $t0, $t1

26. – 26 – CSCE 212H Spring 2011 Shift Instructions Shift left-logical: 00101001 2 by 2 10 => 10100100 2 Multiply 41 10 by 2 2 10 = 164 10 Shift right-logical: 00101001 2 by 2 10 => 00001010 2 Divide 41 10 by 2 2 10 (round down) = 10 10 Shift right-arithmetic 11110101 2 by 2 10 => 11111101 2 Divide -11 10 by 2 2 10 (round down) = -3 10 Amount (0-31) is encoded in SHAMT field for SLL, SRL, SRA Held in a register (rs field) for SLLV, SRLV, SRAV

27. – 27 – CSCE 212H Spring 2011 Load and Store Memory units: word (32 bits, 4 bytes) halfword (16 bits, 2 bytes) byte (8 bits) Assume f, g, h, i, j are stored as words and contiguously la $t2, f lw $s1,4($t2) lw $s2,8($t2) lw $s3,12($t2) lw $s4,16($t2) … sw $s0,0($t2) Similar instructions: –lh, lhu, lb, lbu –sh, sb

28. – 28 – CSCE 212H Spring 2011 Encoding I-Type Load/Store SW $2, 128($3) I-type memory address instruction Opcode is 101011, rs=00011, rt=00010, imm=0000000010000000 101011 00011 00010 0000000010000000

29. – 29 – CSCE 212H Spring 2011 Branch Instructions Branch and jump instructions are required for program control if-statements loops procedure calls Unconditional branch b Conditional branch beq, bgez, bgezal, bgtz, blez “and-link” variants write address of next instruction into $31 (only if branch is taken) Branch targets are 16-bit immediate offset (offset in words)

30. – 30 – CSCE 212H Spring 2011 Encoding I-Type Branch BEQ $3, $4, 4 I-type conditional branch instruction Opcode is 000100, rs=00011, rt=00100, imm=4 (skips next 4 instructions) 000100 00011 00100 0000000000000100Note: bltz, bltzal, bgez, bgezal all have opcode 1, func in rt field

31. – 31 – CSCE 212H Spring 2011 Jump Instructions Unconditional branch Two types: R-type and J-type JR $31 JALR $3 R-type jump instruction Opcode is 0’s, rs=3, rt=0, rd=31 (by default), func=001001 000000 00011 00000 11111 00000 001001 J 128 J-type pseudodirect jump instruction Opcode is 000010, 26-bit pseudodirect address is 128/4 = 32 000010 00000000000000000000100000

32. – 32 – CSCE 212H Spring 2011 MIPS Addressing Modes MIPS addresses register operands using 5-bit field Example: ADD $2, $3, $4 MIPS addresses branch targets as signed instruction offset relative to next instruction (“PC relative”) in units of instructions (words) held in 16-bit offset in I-type Example: BEQ $2, $3, 12 Immediate addressing Operand is help as constant (literal) in instruction word Example: ADDI $2, $3, 64

33. – 33 – CSCE 212H Spring 2011 MIPS Addressing Modes (con’t) MIPS addresses jump targets as register content or 26-bit “pseudo-direct” address Example: JR $31, J 128 MIPS addresses load/store locations base register + 16-bit signed offset (byte addressed) Example: LW $2, 128($3) 16-bit direct address (base register is 0) Example: LW $2, 4092($0) indirect (offset is 0) Example: LW $2, 0($4)

34. – 34 – CSCE 212H Spring 2011 Integer Multiply and Divide mult $2, $3 result in hi (32 bits) and lo (32 bits) mul $2, $3, $4 is psuedo (low 32 bits) madd $2, $3 – multiply and accumulate in hi and lo div $2, $3 quotient in lo and reminder in hi div $2, $3, $4 is psuedo (quotient)

35. – 35 – CSCE 212H Spring 2011 Pseudoinstructions Some MIPS instructions don’t have direct hardware implementations Ex: abs $2, $3 Resolved to: »bgez $3, pos »sub $2, $0, $3 »j out »pos: add $2, $0, $3 »out: … Ex: rol $2, $3, $4 Resolved to: »addi $1, $0, 32 »sub $1, $1, $4 »srlv $1, $3, $1 »sllv $2, $3, $4 »or $2, $2, $1

36. – 36 – CSCE 212H Spring 2011 Lecture Outline Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

37. – 37 – CSCE 212H Spring 2011 Complex Arithmetic Example z=(a*b)+(c/d)-(e+f*g); lw $s0,a lw $s1,b mult $s0,$s1 mflo $t0 lw $s0,c lw $s1,d div $s0,$s1 mflo $t1 add $t0,$t0,$t1 lw $s0,e lw $s1,f lw $s2,g mult $s1,$s2 mflo $t1 add $t1,$s0,$t1 sub $t0,$t0,$t1 sw $t0,z

38. – 38 – CSCE 212H Spring 2011 If-Statement if ((a>b)&&(c==d)) e=0; else e=f; lw $s0,a lw $s1,b bgt $s0,$s1,next0 b nope next0:lw $s0,c lw $s1,d beq $s0,$s1,yup nope:lw $s0,f sw $s0,e b out yup:xor $s0,$s0,$s0 sw $s0,e out:…

39. – 39 – CSCE 212H Spring 2011 For Loop for (i=0;i<a;i++) b[i]=i; lw $s0,a li $s1,0 loop0:blt $s1,$s0,loop1 b out loop1:sll $s2,S1,2 sw $s1,b($s2) addi $s1,$s1,1 b loop0 out:…

40. – 40 – CSCE 212H Spring 2011 Pre-Test While Loop while (a<b) { a++;} lw $s0,a lw $s1,b loop0:blt $s0,$s1,loop1 b out loop1:addi $s0,Ss0,1 sw $s0,a b loop0 out:…

41. – 41 – CSCE 212H Spring 2011 Post-Test While Loop do { a++; } while (a<b); lw $s0,a lw $s1,b loop0:addi $s0,$s0,1 sw $s0,a blt $s0,$s1,loop0 …

42. – 42 – CSCE 212H Spring 2011 Complex Loop for (i=0;i<n;i++) a[i]=b[i]+10; li $2,$0# zero out index register (i) lw $3,n# load iteration limit sll $3,$3,2# multiply by 4 (words) la $4,a# get address of a (assume < 2 16 ) la $5,b# get address of b (assume < 2 16 ) j test loop:add $6,$5,$2# compute address of b[i] lw $7,0($6)# load b[i] addi $7,$7,10# compute b[i]=b[i]+10 add $6,$4,$2# compute address of a[i] sw $7,0($6)# store into a[i] addi $2,$2,4# increment i test:blt $2,$3,loop# loop if test succeeds

43. – 43 – CSCE 212H Spring 2011 Lecture Outline Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

44. – 44 – CSCE 212H Spring 2011 SPIM

45. – 45 – CSCE 212H Spring 2011 SPIM ASM file must be edited with text editor Must have main label Must jr $31 at end Use.data and.text to specify sections Load source file into SPIM Run, step, or use breakpoints Appendix A is good reference In-class example: ASCII to binary conversion

46. – 46 – CSCE 212H Spring 2011 Example Code.data mystr:.asciiz"2887".text main:addi $s0,$0,0# initialize $s0 (current value) addi $s1,$0,0# initialize $s1 (string index) addi $s3,$0,10# initialize $s3 (value 10) loop:lb $s2,mystr($s1)# load a character from string beqz $s2,done# exit if it's the NULL character mul $s0,$s0,$s3# multiply current value by 10 addi $s2,$s2,-48# subtract 48 from character (convert to binary) add $s0,$s0,$s2# add converted value to current value addi $s1,$s1,1# add one to index b loop# loop done:jr $31# return to OS

47. – 47 – CSCE 212H Spring 2011 Lecture Outline Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

48. – 48 – CSCE 212H Spring 2011 Procedures JAL, JALR, and BGEZAL are designed to call subroutines Return address is linked into $31 ($ra) Need to: save the return address on a stack to save the return address save the state of the callee’s registers on a stack have a place for arguments have a place for return value(s)

49. – 49 – CSCE 212H Spring 2011 Memory Allocation

50. – 50 – CSCE 212H Spring 2011 The Stack Stack is designed to hold variable-sized records Stack grows down Normally the old $fp must be stored in the AR to pop Don’t need $fp for fixed-sized AR’s

51. – 51 – CSCE 212H Spring 2011 A Simple Procedure Calling Convention Caller: Place arguments in $a0 - $a3 (limit to 4) Jump-and-link or branch-and-link to subroutineCallee: Pushes an activation record onto the stack (decrement $sp) Save the return address ($ra) on the AR Save registers $s0 - $s7 on the AR Perform computation Save return values to $v0 and $v1 Restore $s0 - $s7 Restore $ra JR $raCaller: Reads $v0 and $v1 and continues

52. – 52 – CSCE 212H Spring 2011 Notes This convention: Limited to 4 arguments and 2 return values (bad!) Doesn’t save $t0 - $t9, $v0 - $v1, and $a0 - $a3 (bad!) Doesn’t allow (variable-size) space on the AR for argument list (saves regs) Doesn’t allow (variable-size) space on the AR for callee’s local variables (bad!) Doesn’t allow space on the AR for return value (saves regs) Fixed AR size (good!) Doesn’t require the caller to prepare and/or teardown the AR (good!)

53. – 53 – CSCE 212H Spring 2011 Stack Example

54. – 54 – CSCE 212H Spring 2011 A Simple Procedure Calling Convention comp:… add $s0,$s1,$s2 jal fact fact:add $sp,$sp,-36 sw $s0,0($sp) sw $s1,4($sp) … sw $ra,32($sp) … lw $s0,0($sp) lw $s1,4($sp) … lw $ra,32($sp) add $sp,$sp,36 jr $ra ( instruction after jal fact) $ra for comp $sn for comp ’s caller $sp $sp+36 $ra for comp $sn for comp ’s caller $sp+36 $sp+72 $ra for fact $sn for comp caller $sp

55. – 55 – CSCE 212H Spring 2011 Example fact: slti$t0,$a0,3# test for n < 3 beq$t0,$zero,L1# if n >= 1, go to L1 addi$v0,$zero,2# return 2 jr$ra# return L1: addi$sp,$sp,-8# allocate space for 2 items sw$ra,4($sp)# save return address sw$a0,0($sp)# save argument addi$a0,$a0,-1# set argument to n-1 jalfact# recurse lw$a0,0($sp)# restore original argument lw$ra,4($sp)# restore the return address addi$sp,$sp,8# pop 2 items mul$v0,$a0,$v0# return value = n * fact(n-1) -glad we saved $a0 jr$ra# go back to caller

56. – 56 – CSCE 212H Spring 2011 Lecture Outline Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

57. – 57 – CSCE 212H Spring 2011 I/O I/O is performed with reserved instructions / memory space Performed by the operating system on behalf of user code Use syscall instruction Call code in $v0 and argument in $a0 Return value in $v0 (or $f0) SPIM services:

58. – 58 – CSCE 212H Spring 2011 Example.data str:.asciiz“the answer = “.text li$v0,4 la$a0, str syscall li$v0,1 la$a0,5 syscall

59. – 59 – CSCE 212H Spring 2011 Example Exercise Copy words from the address in register $a0 to the address in register $a1, counting the number of words in $v0 Stops when 0 is read Do not preserve $a0, $a1, $v0 Terminating word should be copied but not counted addi $v0, $zero, 0 loop:lw $v1, 0($a0) sw $v1, 0($a1) addi $a0, $a0, 4 addi $a1, $a1, 4 beq $v1, $zero, loop

60. – 60 – CSCE 212H Spring 2011 Example Exercise Translate from binary to assembly: AE0B00048D080040 Change MIPS: 8 registers 10 bit immediate constants What is the new size of R and I type instructions?

61. – 61 – CSCE 212H Spring 2011 Example Exercise Extract the bits from field in register $t0 and place them into the least significant bits of $t1 i = 22, j = 5 31-i bitsi-j bitsj bits field