1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 4 - Layout & Design Rules Spring 2007

2. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules2 Announcements  Reading  Wolf 2.4-2.6

3. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules3 Where we are...  Last time:  Transistor Modes of Operation  More about Wires & Vias  Parasitics  Today:  Parasitics continued (Lecture 3 pp. 28-40)  Layout & Design Rules; Stick Diagrams  Discuss Lab 3

4. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules4 Mask Generation  Mask Design using Layout Editor  user specifies layout objects on different layers  output: layout file  Pattern Generator  Reads layout file  Generates enlarged master image of each mask layer  Image printed on glass reticle  Step & repeat camera  Reduces & copies reticle image onto mask  One copy for each die on wafer  Note importance of mask alignment

5. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules5 Symbolic Mask Layers  Key idea:  Reduce layers to those that describe design  Generate physical layers as needed  Magic Layout Editor: "Abstract Layers”  metal1 (blue) - 1st layer metal (equiv. to physical layer)  Poly (red) - polysilicon (equivalent to physical layer)  ndiff (green) - n diffusion (combination of active, nselect)  ntranistor (green/red crosshatch) - combined poly, ndiff  pdiff (brown) - p diffusion (combination of active, pselect)  ptransistor (brown/red crosshatch) - combined poly, pdiff  contacts: combine layers, cut mask

6. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules6 About Magic  Scalable Grid for Scalable Design Rules  Grid distance:  lambda)  Value is process-dependent:  = 0.5 X minimum drawn transistor length  Painting metaphor  Paint squares on grid for each mask layer  Layers to interact to form components (e.g. transistors)

7. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules7 Mask Layers in Magic  Poly (red)  N Diffusion (green)  P Diffusion (brown)  Metal (blue)  Metal 2 (purple)  Well (cross-hatching)  Contacts (X)

8. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules8 Magic User-Interface  Graphic Display Window  Cursor  Box - specifies area to paint  Command window (not shown)  accepts text commands :paint poly :paint red :paint ndiff :paint green :write  prints error & status messages Cursor Box Paint (poly) Paint (pdiff) Paint (ntransistor)

9. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules9 Layer Interaction in Magic  Transistors - where poly, diffusion cross  poly crosses ndiffusion - ntransistor  poly crosses pdiffusion - ptransistor  Vias - where layers connect  Metal 1 connecting to Poly - polycontact  Metal 1 connecting to P-Diffusion (normal) - pdc  Metal 1 connecting to P-Diffusion (substrate contact) - psc  Metal 1 connecting to N-Diffusion (normal) - ndc  Metal 1 connecting to N-Diffusion (substrate contact) - nsc  Metal 1 connecting to Metal 2 - via

10. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules10 Magic Layers - Example nwell nsc psc p-transistor ntransistor metal1 poly ndc polycontact pdc

11. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules11 Lab 2 - Introduction to Magic  Preparation  Read Prof. Stine’s Magic Tutorial  Read Magic Tutorials 1 & 2  In the Lab  Use the PCs running Linux - log in with CS account  Do “Step by Step Example” in Magic Tutorial  Create a layout for a 3-input NAND gate  Plot and hand in

12. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules12 Design Rules  Motivation: Fabrication is not exact  Too much material - “bloat”  Too little material - “shrinkage”  Misalignment  Typical rules:  Minumum size  Minimum spacing  Alignment / overlap  Composition  Negative features

13. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules13 Types of Design Rules  Scalable Design Rules (e.g. SCMOS)  Based on scalable “coarse grid” - (lambda)  Idea: reduce value for each new process, but keep rules the same Key advantage: portable layout Key disadvantage: not everything scales the same  Not used in “real life”  Absolute Design Rules  Based on absolute distances (e.g. 0.75µm)  Tuned to a specific process (details usually proprietary)  Complex, especially for deep submicron  Layouts not portable

14. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules14 SCMOS Design Rules  Intended to be Scalable  Original rules: SCMOS  Submicron: SCMOS-SUBM  Deep Submicron: SCMOS-DEEP  Pictorial Summary: Book Fig. 2-26, p. 80  Authoritative Reference: www.mosis.org

15. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules15 SCMOS Design Rule Summary  Line size and spacing:  metal1: Minimum width=3, Minimum Spacing=3  metal2: Minimum width=3, Minimum Spacing=4  poly: Minimum width= 2, Minimum Spacing=2  ndiff/pdiff: Minimum width= 3, Minimum Spacing=3  minimum ndiff/pdiff seperation=10  wells: minimum width=10, min distance form well edge to source/drain=5  Transistors:  Min width=3  Min length=2  Min poly overhang=2

16. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules16 SCMOS Design Rule Summary  Contacts (Vias)  Cut size: exactly 2 X 2  Cut separation: minimum 2  Overlap: min 1 in all directions  Magic approach: Symbolic contact layer min. size 4 X 4  Contacts cannot stack (i.e., metal2/metal1/poly)  Other rules  cut to poly must be 3 from other poly  cut to diff must be 3 from other diff  metal2/metal1 contact cannot be directly over poly  negative features must be at least 2 in size  CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal

17. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules17 Design Rule Checking in Magic  Design violations displayed as error paint  Find which rule is violated with ":drc why” Poly must overhang transistor by at least 2 (MOSIS rule #3.3)

18. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules18 Stick Diagrams  Key idea: "Stick figure cartoon" of a layout  Useful for planning layout  relative placement of transistors  assignment of signals to layers  connections between cells  cell hierarchy

19. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules19 Stick Diagrams (cont'd)

20. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules20 Stick Diagram Examples

21. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules21 Stick Diagram Examples

22. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules22 Example: Layout / Stick Diagram  Create a layout for a NAND gate given constraints:  Use minimum-size transistors  Assume power supply lines “pass through” cell from left to right at top and bottom of cell  Assume inputs are on left side of cell  Assume output is on right side of cell  Optimize cell to minimize width  Optimize cell to minimize overall area

23. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules23 Layout Example Circuit Diagram. Exterior of Cell

24. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules24 Example - Stick Diagrams Circuit Diagram. Pull-Down Network (The easy part!) Alternatives - Pull-up Network Complete Stick Diagram

25. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules25 Example - Magic Layout  Overall Layout: 52 X 16

26. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules26 Lab 3 - Layout from Stick Diagrams  Design an AOI-22 gate  Logic function: (A*B + C*D)’  Follow the constraints given in the lab handout  Start with a stick diagram  Create a Magic layout  Minimize height and overall area  Hand in “flea” plot marked with dimensions at end of lab  Hand in “Technical Memorandum” w/ plot in lab next week.

27. ECE 425 Spring 2007Lecture 4 - Layout & Design Rules27 Coming Up:  Hierarchical Layout  Review: Levels of Abstraction  More Layout CAD Tools: Extraction, LVS  ASIC Layout Styles