1. Advanced Encryption Standard For Smart Card Security Aiyappan Natarajan David Jasinski Kesava R.Talupuru Lilian Atieno Advisor: Prof. Wayne Burleson

2. Outline  Introduction  System Architecture  Encryption  Decryption  Goals  Work Plan & Schedule

3. Introduction  Security in Smart Cards - Cryptography  Applications Identification Cards Credit Cards  Algorithms Used Rijndael DES(Data Encryption Standard) RSA(Ronald, Samir and Adleman)

4. Processor FSM EncryptKey Sched I/P FSM O/P FSM 16 I/P 256 16 O/P 256 clk Reset clk Reset Ready O/P Request O/P ISA Req I/P Ready I/P clk Reset Key Sub key Overall Block Diagram

5. Encryption Sub Bytes( ) Transformation Shift Rows( ) Transformation Mix Columns( ) Transformation Add Round Key( ) Transformation Key Expansion

6. Key Add SubstitutionShift RowMix ColumnKey Add SubstitutionShift RowKey Add Sub Key ED Raw Data Encryption Algorithm Flow Sub Key Repeat (Round-1) times

7. Decryption Inverse Shift Rows( )Transformation Inverse Sub Bytes( )Transformation Add Round Key( )Transformation Inverse Mix Columns( )Transformation

8. Goals  Hardware Implementation of the Rijndael algorithm using Verilog HDL  Functional Verification of the code with the help of the available test vectors  Synthesis of Verilog Code  Verification of the functionality of the synthesized structure  Speed and Area Estimations

9. Work Plan & Schedule  Kesava & Lilian – Encryption & Decryption Core  David – Key Expansion Module  Aiyappan – I/P & O/P Controller, Processor FSM  Behavioral Model – March 10 th  RTL model – April 20 th  Synthesis – April 30 th  Verification – May 15 th

10. References  Draft of AES - Federal Information Processing Standards Publication, Washington D.C.  Kuo, Henry and Ingrid Verbauwhede- Architectural Optimization for a 1.82Gbits/sec VLSI implementation of the AES Rijndael Algorithm  Rankl and W.Effing- Smart Card Handbook, Second Edition, Chichester, England, John Wiley & Sons Ltd.,2000