1. Compilation & linkage.h read.h.c read.c.c main.c.c list.c.h list.h prog1 Linkage: g++ read.o main.o list.o –o prog1.o main.o.o list.o.o read.o Compilation: g++ -c read.c main.c list.c

2. Compilation & linkage.h read.h.c read.c.c main.c.c list.c.h list.h prog1.o main.o.o list.o.o read.o u If only one file is modified, do we have to recompile all over again? u No. The Makefile uses the dependencies graph

3. Compilation & linkage.h read.h.c read.c.c main.c.c list.c.h list.h prog1.o main.o.o list.o.o read.o u If read.h is modified, what should be done? u We have to recreate only a subset of the files!

4. Make u Make is a program who’s main aim is to update other programs in a “smart” way. u “smart” =  Build only out-of-date files (use timestamps).  Use the dependency graph for this. u You tell make what to do by writing a “makefile”

5. What makefile contains u Explicit rules u Implicit rules u Variable definitions u Directives u Comments

6. Explicit rules u Rule Syntax: targets : prerequisites command... u Targets: Usually files u Prerequisites: Other files that the targets depend on u Command: What to execute (shell command)  tells make it’s a command

7. Example.h read.h.c read.c.c main.c.c list.c.h list.h prog1.o main.o.o list.o.o read.o Makefile example: prog1: read.o main.o list.o g++ main.o read.o list.o –o prog1 main.o: main.c read.h list.h g++ -c main.c read.o: read.c read.h g++ -c read.c list.o: list.c list.h g++ -c list.c

8. makefile names u make looks automatically for : makefile, Makefile u Override by using –f : make –f MyMakefile

9. How Make works? Make works as follows: u Given a target:  Find the rule for it  Check if the rule prerequisites are up to date  By “recursive” application on each of them  If one of the prerequisites is newer than target, run the command in rule body.

10. Example Makefile: prog1: read.o main.o list.o g++ main.o read.o list.o –o prog1 main.o: main.c read.h list.h g++ -c main.c read.o: read.c read.h g++ -c read.c list.o: list.c list.h g++ -c list.c Running make: make prog1 read.h modified u Check prog1  Check read.o Do: g++ -o read.c  Check: main.o Do: g++ -o main.c  Target: list.o Do: Do: g++ main.o read.o list.o –o prog1

11. Comments # comments are easy

12. Variables Make maintains variables  Case sensitive  Traditionally – use capital letters FOO = 1 CFLAGS = -g TARGETS = list.o main.o read.o Rules can use variables main.o: main.c read.h list.h g++ $(CFLAGS) –c main.c

13. Automatic Variables Set automatically by Make, depend on current rule u $@ - target u $^ - list of all the prerequisites  including the directories they were found u $< - first prerequisite in the prerequisite list.  $< is often used when you want just the.c file in the command, while the prerequisites list contains many.h too u $? - all the prerequisites that are newer than the target u Many Others …….

14. Setting Variables u Using “=“ will expend variables recursively: CFLAGS = $(include_dirs) –O include_dirs = -Ifoo -Ibar u This means you cant do: CFLAGS = $(CFLAGS) -O #error ! You can append to it instead: CFLAGS += -O u You can override variables when you run make: make CFLAGS='-g -O''

15. Using Wildcards u Automatic Wildcard (*,?) expansion in:  Targets  Prerequisites  Commands clean: rm -f *.o # good objects = *.o # no good # instead use wildcard function # of make objects := $(wildcard *.o) # good

16. Implicit rules  We saw “explicit rules” so far, e.g: list.o: list.c list.h g++ -c list.c u Implicit rules (many kinds):  Example, creation by suffices. Create “.o” files from “.c” files.c.o: $*.c g++ -c –o $@ $< $* - the match without the suffix (e.g. list) $@ - file for which the match was made (e.g. list.o) $< - the matched dependency (e.g. list.c)

17. Implicit Rules Now we can write:.c.o: $*.c g++ -c –o $@ $< prog1: read.o main.o list.o g++ main.o read.o list.o –o prog1 main.o: read.h list.h read.o: read.h list.o: list.h u The dependencies of main.o on main.c are specified in the rule u The command is also specified by the rule

18. Where make finds Prerequisites? u Default: current directory u Better design:  separate object & binaries from source code  Use variable VPATH to look for prerequisites. u You can set it in the makefile start to several directories: VPATH = src:../headers #separate by “:” u There is also vpath (lower case!) which make uses for paths for specific file types. Read Manual.

19. Auto variables & Directory Search u Commands are executed by the shell. You must be carefull the shell will find what make found. Use $^ for this VPATH = src:../headers foo.o : foo.c defs.h hack.h cc -c $(CFLAGS) $< -o $@ Note that foo.c might be actually src/foo.c u $@ expands to full pathname This version will not work: foo.o : foo.c defs.h hack.h cc -c $(CFLAGS) foo.c -o $@

20. Directory Search for Link Libraries u Example: foo : foo.c -lcurses cc $^ -o $@ u “-lname” tells make that name is a library.  Library name expansions are set by the.LIBPATTERNS variable. u Default is: “lib%.so lib%.a” replace % with lib name. u This means make first looks for libname.so then for libname.a. u The path in which it looks for liberaries is: current, VPATH, vpath, /lib, /usr/lib/

21. Built In Implicit Rule u Make has a set of default implicit rules for compiling  C  C++  Fortran  … u Built-in implicit rules make liberal use of certain predefined variables u command used to compile a C source file actually says `$(CC) -c $(CFLAGS) $(CPPFLAGS)'

22. Variables Controling Built-in Commands u Name of programs  CC - Program for compiling C programs  CXX Program for compiling C++ programs u Arguments for programs: CFLAGS Extra flags to give to the C compiler.  CPPFLAGS Extra flags to give to the C preprocessor and programs that use it (the C and Fortran compilers).  CXXFLAGS Extra flags to give to the C++ compiler. LDFLAGS Extra flags to give to compilers when they are supposed to invoke the linker, `ld'.

23. Implicit Rules Revisted u Suffix Rules (old !):.c.o: $(CC) -c $(CFLAGS) $(CPPFLAGS) -o $@ $< u Suffix rules cannot have any prerequisites of their own:.c.o: foo.h # won’t work as you expect!!! $(CC) -c $(CFLAGS) $(CPPFLAGS) -o $@ $< u Suffix rules use.SUFFIXES from suffix. You can add to it by doing:.SUFFIXES:.hack.win

24. Implicit Rules Revisted u You might prefer to work with a Pattern rule: %.o: %.c foo.h $(CC) -c $(CFLAGS) $(CPPFLAGS) -o $@ $< u Here you can also use empty commands, as it uses the defaults ones. u Control the default by changing the variables %.o: %.c foo.h # this is the same as above !

25. Phony Targets clean: rm *.o temp u Target not really the name of a file. No file will be created. u What happens when there is a “clean” file in our path? u.PHONY is a built in target name. Its list of prerequisites tells make which targets should not be treated as files.

26. Phony clean u This will work even “clean” file actually exist:.PHONY: clean clean: rm *.o temp u When one phony target is a prerequisite of another, it serves as a subroutine of the other.PHONY: cleanall cleanobj cleanall : cleanobj cleandiff rm program cleanobj : rm *.o

27. Phony all u If no target is specified make executes the first explicit rule it finds. u It is common to name it “all”. This is usually used to build all possible programs that are in the makefile with just one make call. all : prog1 prog2 prog3.PHONY : all prog1 : prog1.o utils.o cc -o prog1 prog1.o utils.o prog2 : prog2.o cc -o prog2 prog2.o

28. Writing Rules A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and commands to use to create or update the target. The order of rules is not significant, except for determining the default goal: the target for make to consider, if you do not otherwise specify one. The default goal is the target of the first rule in the first makefile. If the first rule has multiple targets, only the first target is taken as the default. There are two exceptions: a target starting with a period is not a default unless it contains one or more slashes, `/', as well; and, a target that defines a pattern rule has no effect on the default goal. (See section Defining and Redefining Pattern Rules.)Defining and Redefining Pattern Rules Therefore, we usually write the makefile so that the first rule is the one for compiling the entire program or all the programs described by the makefile (often with a target called `all'). See section Arguments to Specify the Goals. Arguments to Specify the Goals

29. Rule Syntax targets : prerequisites command...