1. CHAPTER 7 ASSEMBLY LANGUAGE INSTRUCTIONS
7.1 Introduction
7.2 Data Transfer Instructions
7.3 Arithmetic Instructions
7.4 Bit Shifting Instructions
7.5 Looping Instructions
7.6 Unconditional Transfer Instructions
7.7 Conditional Jump Instructions
7.8 Other Instructions

2. Introduction
Intel processor using 8 addressing modes (refer to chapter 5.4)
Immediate addressing
- for instructions with two operands, the first operand may be a register or memory location, and the second operand may be an immediate constant. First operand defines the length of second operand. Examples:
BYTE_VAL DB 150 ; Define byte
WORD_VAL DW 300 : Define word …
SUB BYTE_VAL, 50 ; Immediate to memory (byte)
MOV WORD_VAL, 40H ; Immediate to memory (word)
MOV AX, 0245H ; Immediate to register (word)
1st operand -- memory or register
2nd operand – immediate constant

3. Introduction Register addressing (registerregister)
- depending on the instruction, the register may appear in the first operand, the second operand or both. Examples:
MOV DX, WORD_VAL ; Register in the first operand
MOV BYTE_VAL, AL ; Register in the second operand
MOV DX, CX ; Registers in both operands
Direct Memory addressing (registermemory)
- in this mode, one of the operands references a memory location and the other operand references a register. Examples:
ADD BYTE_VAL, DL ; Add register to memory (byte)
MOV BX, WORD_VAL ; Move memory to register (word)

4. Introduction Direct-offset addressing
- a variation of direct memory mode, uses arithmetic operation to modify an address. Example:
BYTE_TBL DB 12, , 18, 20, ……. ; Table of Byte …
MOV CL, BYTE_TBL[2] Or
MOV CL, BYTE_TBL+2
the first MOV uses an arithmetic operator to access the third byte (value 16) whereas the second MOV uses a plus (+) operator for exactly the same effect.

5. Introduction Indirect memory addressing
takes advantages of computer’s capability for segment:offset addressing.
the registers used for this purpose are:
 base registers, BX and BP
 index registers, DI and SI
these registers will be coded within square brackets that indicate a reference to memory.
Examples:
ADD CL, [BX] ; 2nd operand = DS:BX
ADD [BP], CL ; 1st operand = SS:BP
MOV CX, DS:[38B0H] ; word in memory at offset 38B0H

6. Introduction Base displacement addressing
- In this mode, the content in the base registers (BX and BP) or the index registers (DI and SI) will be combined with the displacement (offset) value to form an effective address. Examples:
ADD CL, [DI+2] ; DI offset plus 12
SUB DATA_TBL[SI], 25 ; SI contains offset
MOV DATA_TBL[DI], DL ; DI contains offset

7. Introduction Base-index addressing
- In this mode, the content in base registers (BX or BP) will be added with the content in the index registers (DI or SI) to obtain the real address of the data. For example, [BX+DI] means the address BX plus the address in DI. Examples:
MOV AX, [BX+SI] ; move word from memory
ADD [BX+DI], CL ; Add byte to memory

8. Introduction Base-index with displacement addressing
The content in base register will be added with the content in the index registers and also the displacement (offset) value to obtain the address of the data. Examples:
MOV AX, [BX+DI+10]
MOV CL, DATA_TBL[BX+DI] ;
or [BX+DI+DATA_TBL]

9. Introduction
Symbolic language for Intel processor family can be categorized into:
arithmetic
ASCII-BCD conversion
Bit shifting
comparison
data transfer
flag operation
input/output
logic operation
looping
processor control
stack operations
string operations
transfer (conditional and unconditional)
type conversion
Note: To know the symbols for each instruction in detail, refer to Chapter 6 (IBM PC Assembly Language and Programming – Peter Abel). This course will only explain a part of the above category.

10. Data Transfer Instructions
There are a couple of instructions categorized as data transfer instructions, such as LOAD, MOVE, EXCHANGE and TRANSLATE. Below are a few examples of these instructions.
MOV Instruction
MOV is a 2-address instruction (refer to chapter 5). This instruction will transfer data from second address field into the first address field. The content in second address field will remain unchanged. Both fields must be of same size (whether both are byte, word or double word). The Format for MOV:
[Label :]
MOV
register/memory , register/memory/immediate
move

11. Data Transfer Instructions
Some examples on MOV:
BYTEFLD DB ? ; define byte
WORDFLD DW ? ; define word …
MOV EDX , ECX ; register to register
MOV BYTEFLD , DH ; register to memory
MOV WORDFLD , 1234 ; immediate to memory
MOV CH , BYTEFLD ; memory to register
MOV CX , 40H ; immediate to register
MOV AX , DS ; segment register to register

12. Data Transfer Instructions
Move-and-Fill Instructions: MOVSX and MOVZX
For the MOV instruction, size of source and destination must be same (eg, byte-to-byte, word-to-word). For MOVSX and MOVZX instructions facilitate transferring data from a byte or word source to a word or doubleword destination. Format for MOVSX and MOVZX instructions:
[Label:]
MOVSX/MOVZX
register/memory,register/memory/immediate

13. Data Transfer Instructions
MOVSX
used with signed arithmetic value.
moves a byte or word to destination with size of word or
double word and all the leftmost bits of destination will be
filled with the sign bit.
MOVSX CX, B ; CX =
MOVZX
used with unsigned arithmetic value
double word and the leftmost bit of destination will be filled
with the value 0.
MOVZX CX, B ; CX =

14. Data Transfer Instructions
Examples:
MOVSX AX, B ; AX =
MOVZX AX, B ; AX =

15. Data Transfer Instructions
XCHG Instruction
This instruction is used to change the value of source into that of the destination and vice versa. The format for this instruction:
Example:
WORDQ DW ? ; Word data item
. . .
XCHG CL , BH ; exchange the content of the 2 registers
XCHG CX, WORDQ ; exchange the content between register
; and memory
[Label :]
XCHG
register/memory, register/memory

16. Data Transfer Instructions
LEA Instruction
This instruction is useful for initializing a register with an
offset address. Its format is
Usually, LEA is used to initialize an offset in BX, DI or SI registers as
index address in memory.
DATATBL DB 25 DUP (?) ; Table for 25 bytes
BYTEFLD DB ? ; one byte
. . .
LEA BX, DATATBL ; Enter the offset address
MOV BYTEFLD, [BX] ; Transfer the first byte for
; DATATBL
[Label:]
LEA
register, memory

17. Arithmetic Instructions – Processing Binary Data
IBM PC has 2 sets of arithmetic instructions, for binary data and for data in ASCII or BCD data. This chapter will only discuss the arithmetic instructions for binary data. Instructions that involve in arithmetic operations for binary data are shown in Table 7.1. This chapter will only cover a part of these instructions.

18. Arithmetic Instructions – Processing Binary Data
Description
ADC
Add with carry
IDIV
Divide signed
ADD
Add
IMUL
Multiply signed
CBW
Convert byte to word
MUL
Multiply unsigned
CDQ
Convert doubleword to quadword
NEG
Negate
CWD
Convert word to doubleword
SBB
Subtract with borrow
CWDE
Convert word to extended doubleword
SUB
Subtract
DIV
Divide unsigned
Table 7.1

19. Arithmetic Instructions – Processing Binary Data
There are two types of binary data, signed and unsigned. For unsigned data, all bits are intended to be data bits. For signed data, the leftmost bit is a sign bit.
Table 7.2 gives the maximum values for unsigned and signed data according to register width.

20. 7.3.1 Addition and Subtraction Of Binary Data
Format for ADD and SUB instructions: (note: there are no direct memory-to-memory operations)

21. 7.3.1 Addition and Subtraction Of Binary Data
Example of the ADD and SUB instructions:
BYTE1 DB 24H ;Data elements
WORD1 DW 4000H
. . .
MOV CL , BYTE1 ; byte processing
MOV DL , 40H
ADD CL , DL ; register to register
SUB CL , 20H ; Immediate from register
ADD BYTE1 , BL ; register to memory
MOV CX , WORD1 ; word processing
MOV DX , 2000H
SUB CX , DX ; register from register
SUB CX , 124H ; Immediate from memory
ADD WORD1 , DX ; register to memory

22. Exercise
Assume that BYTE1 is defined as DB 05, show the result for the following instructions:
Instruction Before After
MOV CX, 25H CX = 0000H CX=0025
MOV CL, 0 CX = FFFFH CX=FF00
MOV AX, BYTE1 AX=1234H AX=invalid size
ADD DL, BYTE1 DX=0120H DX=0125
XCHG AH,AL AX=1234H AX=3412
SUB CX,CX CX=1234H CX=0000
XCHG CX,CX CX=1234H CX=1234

23. 7.3.2 Multiplying Binary Data
For multiplication process,
MUL instruction is used for unsigned data
IMUL is used for signed data.
Both of these instructions affect the Carry and Overflow flag. The format for MUL and IMUL instructions:
Observe that MUL/IMUL is a one address instruction, hence it requires an the accumulator register to hold operand1 and result (refer Chapter Instruction format) In IBM PC, the AX register (AL/AH/EAX) acts as accumulator.
The multiplication operations are byte times byte, word times word and doubleword times doubleword.

24. Byte Times Byte
For multiplying two one-byte values, the multiplicand (first operand) is in AL register, and the multiplier (second operand) is a byte data in memory or another register that determined by the address field in the MUL/IMUL instruction.
Example: MUL DL
the operation multiplies the content of AL by the contents of DL. The generated product is in AX. The operation ignores and erases any data that may already be in AH.

25. Doubleword Times Doubleword
In this multiplication, the multiplicand is in EAX and the multiplier is a doubleword in the memory or register (according to the addressing more used in the MUL/IMUL instruction). The result will be kept in a pair of EDX:EAX registers :

26. Field Size
Address field in the MUL/IMUL instruction refers only to the multiplier that will determine the field sizes (whether byte, word, or doubleword). The instruction will use the size of the address field (multiplier) to determine the position of the multiplicand whether it is in AL, AX or EAX
A few examples on the MUL instruction together with the multiplier size, multiplicand position and product:

27. Field Size

28. MUL is used for unsigned data
Examples on the usage of the MUL instructions using the data as defined below:
BYTE1 DB 80H
BYTE2 DB 40H
WORD1 DW 8000H
WORD2 DW 2000H
DWORD1 DD H
DWORD2 DD H
(a) MOV AL, BYTE1 ; AL (multiplicand)=80H
MUL BYTE2 ; byte x byte, product in AX
; 80H x 40H, AX= 2000H
(b) MOV AX, WORD1 ; AX (multiplicand)=8000H
MUL WORD2 ; word x word, product in DX:AX
; 80000H x 2000H,
; DX:AX= H

29. Example 1 : (MUL Instruction)
MOV AL, BYTE1
MUL BYTE2 ; byte x byte, product in AX
in the above example, 80H (128) is multiplied with 40H (64) and the result is 2000H (8,192) kept in AX register.
MOV AX, WORD1
MUL WORD2 ; word x word, product in DX:AX
in the above example, 8000H is multiplied with 2000H and the result, H is kept in a pair of registers, DX:AX.

30. IMUL is used with signed data
Examples on the usage of the IMUL instructions using the data as defined below:
BYTE1 DB 80H
BYTE2 DB 40H
WORD1 DW 8000H
WORD2 DW 2000H
DWORD1 DD H
DWORD2 DD H
(a) MOV AL, BYTE1 ; AL (multiplicand)=80H (-ve value)
IMUL BYTE2 ; byte x byte, product in AX
; 80H (-ve) x 40H (+ve), AX= E000H
(b) MOV AX, WORD1 ; AX (multiplicand)=8000H (-ve value)
IMUL WORD2 ; word x word, product in DX:AX
; 80000H (-ve) x 2000H (+ve),
; DX:AX= F H

31. Example 2 : (Arahan IMUL)
MOV AL, BYTE1
IMUL BYTE2 ; byte x byte, product in AX
in the above example, BYTE1 and BYTE2 is considered as signed data, that is –128 (80H) and +64 (40H) and the result –8192 (E000H) is stored in the AX register
MOV AX, WORD1
IMUL WORD2 ; word x word, product in DX:AX
in the above example, WORD1 and WORD2 is considered as signed data, that is 8000H a is –ve value and 2000H is a +ve value. The result, F H is a–ve value and is kept in a pair of registers, DX:AX.

33. 7.3.3 Dividing Binary Data
For division operation, the DIV instruction is used for unsigned data whereas IDIV is used for signed data. Its format:
The basic divide operations are byte into word, word into doubleword, and doubleword into quadword.

34. Byte into Word
In a division of byte into word, the dividend (first operand) is in the AX register, whereas the divisor (second operand) is a byte data in memory or another register that is defined in the DIV/IDIV instruction. The operation stores the remainder in the AH register and the quotient in the AL register.

35. Word into Doubleword
In this division, the dividend is in a pair of registers, DX:AX, whereas the divisor (operand 2) is a word data in the memory or another register as defined in the DIV/IDIV instruction. This operation will keep the remainder in the DX register and the quotient in the AX register.

36. Doubleword into Quadword
In this division, the dividend is in a pair of registers, EDX:EAX, whereas the divisor is a doubleword data in the memory or another register as defined in the DIV/IDIV instruction. This operation stores the remainder in the EDX register and the quotient in the EAX register. 

37. Field Size
As in MUL/IMUL, address field in the DIV/IDIV instruction refers to the divisor (second operand) that determines the field sizes. The following example shows the divisor is in the register (example 1) and memory (example2) with a certain size.
Example1 : using register addressing mode
Example 2 : using direct addressing mode - divisor is predefined in the memory

38. DIV BYTE1 ;2000H/80H, quotient=40H, remainder=00H
The following are a few examples of the DIV instruction using the data definition below:
BYTE1 DB 80H ; Byte value
BYTE2 DB 16H
WORD1 DW 2000H ; Word value
WORD2 DW 0010H
WORD3 DW 1000H
(a) MOV AX, WORD1 ;AX=2000H
DIV BYTE1 ;2000H/80H, quotient=40H, remainder=00H
;AL=40H, AH=00H
(b) MOV DX, WORD2 ;DX=0010H
MOV AX, WORD3 ;AX=1000H,dividend in DX:AX (WORD2:WORD3)
;DX:AX = H
DIV WORD1 ; H/2000H remainder:quotient in DX:AX
; 1000H:0080H

39. DIV Instruction
MOV AX, WORD1
DIV BYTE1
In the above example, the value 2000H (8092) will be divided with 80H (128), the quotient, 40H (64) will be kept in the AL register while its remainder, 00H will be kept in the AH register.
MOV DX, WORD2
MOV AX, WORD3 ; dividend in DX:AX (WORD2:WORD3)
DIV WORD1 ; remainder:quotient in DX:AX
in the above example, the value H will be divided with 2000H. The remainder, 1000H will be kept in the DX register, whereas its result, 0080H will be kept in the AX register.

40. IDIV BYTE1 ; 2000H(+ve)/80H (-ve), ; quotient=C0H (-ve), remainder=00H
The following are a few examples of the IDIV instruction using the data definition below:
BYTE1 DB 80H ; Byte value
BYTE2 DB 16H
WORD1 DW 2000H ; Word value
WORD2 DW 0010H
WORD3 DW 1000H
(a) MOV AX, WORD1 ; AX=2000H
IDIV BYTE1 ; 2000H(+ve)/80H (-ve), ; quotient=C0H (-ve), remainder=00H
; AL=C0H, AH=00H
(b) MOV DX, WORD2 ;DX=0010H
MOV AX, WORD3 ;AX=1000H,dividend in DX:AX (WORD2:WORD3)
;DX:AX = H (+ve)
IDIV WORD1 ; H (+ve)/2000H (+ve)
;remainder:quotient in DX:AX
;1000H:0080H

41. (using the same data definition)
IDIV Instruction
(using the same data definition)
MOV AX, WORD1
IDIV BYTE1
in the above example, the value WORD1 is a +ve number whereas BYTE1 is a –ve number. If WORD1 is divided with BYTE1, its result will be a –ve number (64 or C0H) will be kept in the AL register whereas its remainder will be kept in the AH.register
MOV DX, WORD2
MOV AX, WORD3 ; dividend in DX:AX (WORD2:WORD3)
DIV WORD1 ; remainder:quotient in DX:AX
in the above example the value H (+ve) will be divided with 2000H (+ve). Its remainder, 1000H (+ve) will be kept in the DX register, whereas its result, 0080H (+ve) will be kept in the AX register.

42. DIV Examples Divide 8003h by 100h, using 16-bit operands:
mov dx,0 ; clear dividend
mov ax,8003h ; dividend
mov cx,100h ; divisor
div cx ; AX = 0080h, DX = 3
Same division, using 32-bit operands:
mov edx,0 ; clear dividend
mov eax,8003h ; dividend
mov ecx,100h ; divisor
div ecx ; EAX = h, EDX = 3

43. Exercise (a) What will be the hexadecimal values of DX, AX?
mov ax,1234h
mov bx,100h
mul bx
DX = 0012h, AX = 3400h
(b) What will be the hexadecimal values of EDX, EAX?
mov eax, h
mov ecx,10000h
mul ecx
EDX = h, EAX = h
(c) What will be the hexadecimal values of DX and AX after the following instructions execute?
mov dx,0087h
mov ax,6000h
div bx
DX = 0000h, AX = 8760h

44. Shifting Instruction

45. SHR/SAR/SHRD: Shifting Bits Right
SHR – shift logical right
SAR – shift arithmetic right

46. Example of the SHR instruction
As in the example above, the SHR instruction will enter the value 0 to the leftmost bit after the shift. Carry flag will contain the last bit shifted out after the shift C BH 1
SHR BH, 01 1
SHR BH, CL 00 1
SHR BH, 02 00 1

47. Example of the SAR instruction
The SAR instruction is used on signed number. SAR will enter the sign bit (whether 0 (+ve) or 1 (–ve)) into the leftmost bit after every shift. Examples of SAR instruction BH 1
SAR BH, 01 1 1
SAR BH, CL 11 1
SAR BH, 02 11 1

48. SHRD Instruction
This instruction is only for and above processors. Its format is as below:
The first operand receives the bits that are shifted.
The second operand is the same size and contains the bits to be shifted.
The third operand (CL or immediate value) contains the shift count.
Examples:
SHRD CX, DX, 4 ; Right shift 4 bits from DX into CX
SHRD ECX, EBX, CL ; Right shift ? bits from EBX into ECX 1 2 3

49. SHL/SAL/SHLR : Shifting Bits Left

50. BH 1 1 00 1 00 1

51. SHL/SAL/SHLR : Shifting Bits Left
Shift left instructions (whether SHL or SAL) will always enter the value of 0 into the rightmost bit after every shift. Shift left instruction is useful in a multiplier operation. Observe in the example above, a 1-bit shift to the left is equivalent to the multiplication of a value with 2, a 2-bit shift to the left is equivalent to the multiplication of a value with 4, and so forth (3 left shifts is equivalent as multiplication with 8,…)
As in SHRD, SHLD is a shifting bit left instruction that is introduced in the and above processors. Its format:
The first operand receives the bits that are shifted. The second operand contains the data that is to be shifted and the third operand ( CL or immediate value) contains shift count. Example:
SHLD BX, DX, 2 ; Left shift 2 bits from DX into BX
SHLD EAX, EDX, CL ; Left shift ? bits from EDX into EAX

52. 3. ROR/RCR: Rotating Bits Right
This instruction will rotate the bit to right. Every bit rotated will enter the carry flag. ROR is for unsigned data whereas RCR is for signed data. Bit movement is as below:

53. A few examples on ROR: 1 2 3
The difference between ROR and RCR is only the way of operation. In RCR, every bit that is rotated will enter the carry flag before entering the leftmost bit 1 BH 1 1 1 2
011 3 1
011

54. 4. ROL/RCL: Rotating Bits Left
ROL/RCL is an operation that will rotate the leftmost bit to the rightmost. Every bit that is rotated will enter the Carry Flag. ROL is for unsigned data whereas RCL is for signed data. The Data movement is depicted as below:

55. Below are instances of the ROL instruction :1 2 3 BH 1 1 1 2 1 1
011 3 1
011

56. 7.5 Looping Instructions (Conditional Transfer Instructions)
The assembler prepares 3 kinds of addressing that are
distinguished by the distance from the current address:
Short address, distance limited to between –128 (80H) to +127 (7FH) bait.
Near address, distance limited to between –32,768 (8000H) to +32,767 (7FFFH) bytes in the same segment
Far address, its distance exceeds 32K byte whether in the same or different segment

57. Looping instructions
There are two types of looping instruction that are LOOP and LOOPxx. Both of these instructions require an initial value in CX. For each iteration, LOOP automatically deducts 1 from CX. Once CX reaches zero, control drops through to the following instruction; if CX is nonzero, control jump to the operand address. LOOPE/LOOPZ (Loop while equal/zero) will continue looping while the CX register is 0 or 0 condition is set. As for the LOOPNE/LOOPNZ (Loop while not equal/zero) instructions, they will continue looping while the value in the CX register is not zero or the zero condition is not set.

59. LOOP Instruction – example using DEBUG
4A66:0100 MOV CX,5 ;LOOP COUNTER=5
4A66:0103 MOV AX,0
4A66:0106 ADD AX,CX
4A66:0108 LOOP 106 ;LOOP TO LOCATION 0106

60. 7.6 Unconditional Transfer Instructions
The following are unconditional transfer instructions:

61. 1. CALL and RET[n] Instructions
CALL instruction is to shift control to the procedure that is called.
RET[n] instruction is to return control to the procedure that made the call. Usually the RET[n] instruction is the last instruction to be executed in the called procedure. Its format:

63. 2. JMP Instruction
The JMP instruction is unconditional. Control will go to the given address in any condition. The Format of the JMP instruction:
Address for the jump instruction can be either short, near or far. The jump instruction also can be to the front or to the back, like the example below:

64. JMP

65. 3. INT instruction enable program to interrupt its own processing
INT exits normal processing and access the Interrupt Vector Table in low memory to determine the address of requested routine.
The operation then transfer to BIOS or OS for specified action and returns to the program to resume processing.
Refer to section for examples of INT instructions.

66. 7.7 Conditional JUMP Instructions
Format for conditional jump (Jnnn) is:
There are varieties of conditional jump instructions that transfer control depending on settings in the flags register: ZF, CF, OF, AF and SF.
Table below shows some example of conditional jump that are used for unsigned data.
The LOOP A20 statement in Table 7.5.3, can be replaced by using the conditional statement, JNZ A20 and DEC CX as in Table

67. Table 7.7.2

68. conditional jump instructions usually used with other instructions: CMP, INC, DEC etc.
the following are examples of conditional jump instruction:

70. 7.8 Other Instructions
Only certain instructions are covered in this course (SAK 3207). Students are encouraged to try other instructions.
Other instructions:
Instructions for processing string data such as, MOVS (move string), CMPS (compare string), LODS (load string) etc.
Instructions for processing different data type, such as ASCII data and BCD data.
Instruction to video and keyboard processing
Etc