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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 426 - VLSI System Design Lecture 9 - ASM Diagrams.

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Presentation on theme: "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 426 - VLSI System Design Lecture 9 - ASM Diagrams."— Presentation transcript:

1 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 426 - VLSI System Design Lecture 9 - ASM Diagrams February 26, 2003

2 2/26/03Lecture 9 - ASM Diagrams2 Announcements  Reading: Wolf 8.3  MOSIS Chips are IN!  Breaking News: Intel’s “Prescott” Pentium 4 discussed at Intel Developer’s Forum  90nm process technology  Clock >3GHz (up to 5GHz w/ anticipated process improv.)  1 Mbyte L2 Cache  800 MHz front-side bus  Strained Silicon  13 new instructions Source: EE Times 2/24/03

3 2/26/03Lecture 9 - ASM Diagrams3 Where we are...  Last Time  Review - Basic Concepts in Register-Transfer Design  Datapath / Control Paradigm  Testbenches for Register-Transfer Designs  Design Guidelines  ASM Diagrams  Today - Register Transfer Design  ASM Diagrams  Handshaking

4 2/26/03Lecture 9 - ASM Diagrams4 ASM Diagrams  ASM = “Algorithmic State Machine*”  A flowchart notation for state machines  Motivation  High-level description of clock-cycle level behavior  Alternative to traditional state diagrams Easier to read for large diagrams Prevents inconsistent diagram specifications  More concise than Verilog code *Christopher R. Clare, Designing Logic Using State Machines, McGraw-Hill, 1973

5 2/26/03Lecture 9 - ASM Diagrams5 Flavors of ASM Diagrams  Low-level  Cycle-by-cycle timing  Detailed specification of input / output values  Equivalent to standard state diagram  Register-Transfer Level (book uses this)  Cycle-by-cycle timing  Abstract operations (can map directly to low level)

6 2/26/03Lecture 9 - ASM Diagrams6 ASM Elements condition Decision Box Outputs / actions Conditional Output Box Outputs / actions S001 State Box State Name State Code (Optional) Asserted when present (default not asserted) Asserted when present (default not asserted)

7 2/26/03Lecture 9 - ASM Diagrams7 Describing an ASM State RDY START SETB3 CLRB2 CLRB1 CLRB0 WAIT1000 F T Unconditional Output: RDY = 1 Input Condition UNAMBIGUOUS BRANCH Contitional Outputs: if (current state == WAIT1 && START == 1) { SETB3 = 1; CLRB2 = 1; CLRB0 = 1; } Note all other outputs are 0!

8 2/26/03Lecture 9 - ASM Diagrams8 State Description w/ Complex Branches OUT1 IN1 OUT2 S0 F T IN2 S1 OUT3 State Diagram Equivalent (Fill In) S2S1

9 2/26/03Lecture 9 - ASM Diagrams9 ASM Diagram Pitfall  Conditional output boxes specify values  Conditional output boxes don’t specify sequence SETB2 GT CLRB3 TST3 F T INIT TST2 CLK State GT CLRB3

10 2/26/03Lecture 9 - ASM Diagrams10 ASM Example - Successive Approximation Circuit

11 2/26/03Lecture 9 - ASM Diagrams11 ASM Example - Successive Approximation Circuit

12 2/26/03Lecture 9 - ASM Diagrams12 ASM Example:  ASM Diagram for Successive Approximation Circuit RDY START SETB3 CLRB2 CLRB1 CLRB0 WAIT1 F T SETB2 GT CLRB3 TST3 F T SETB1 GT CLRB2 TST2 T SETB0 GT CLRB1 TST1 F T GT CLRB0 TST0 F T

13 2/26/03Lecture 9 - ASM Diagrams13 Example: MIPS Multicycle Design

14 2/26/03Lecture 9 - ASM Diagrams14 Example: MIPS Multicycle Design

15 2/26/03Lecture 9 - ASM Diagrams15 Multicycle Control - ASM Diagram Part 1 MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 IF ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 ID OP 1234 LW, SW RType BEQJ other ? 0

16 2/26/03Lecture 9 - ASM Diagrams16 Multicycle Control -ASM Diagram Part 2 MemRead IorD = 1 LDMEM MemWrite IorD = 1 STMEM 0 RegWrite MemToReg=1 RegDst = 0 LDWB 0 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 ADRCALC OP=LW 1 TF

17 2/26/03Lecture 9 - ASM Diagrams17 Multicycle Control -ASM Diagram Part 3 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RTEX ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 BR 0 RegDst = 1 RegWrite MemtoReg = 0 RTWB 0 2 PCWrite PCSource = 10 JMP 0 34

18 2/26/03Lecture 9 - ASM Diagrams18 RT-Level ASM  Key idea:  Use same notation as regular ASM  Instead of outputs, write register transfers  Advantages  Plan complex designs before details are nailed down  Estimate resource costs by counting operations in each state

19 2/26/03Lecture 9 - ASM Diagrams19 Multicycle Control - ASM Diagram Part 1 A = Reg[Rs] B = Reg[Rt] ALUOut = PC + extend(immed) ID OP 1234 LW, SW RType BEQJ other ? IR = MEM[PC] PC = PC + 4 IF 0

20 2/26/03Lecture 9 - ASM Diagrams20 Multicycle Control -ASM Diagram Part 2 MDR = MEM[ALUOut] LDMEM MEM[ALUOut] = B STMEM 0 Reg[Rt] = MDR LDWB 0 ALUOut = A + extend(immed) ADRCALC OP=LW 1 TF

21 2/26/03Lecture 9 - ASM Diagrams21 Multicycle Control -ASM Diagram Part 3 Reg[Rd] = ALUOut RTWB 0 ALUOut = A op B RTEX 2 if (A==B) PC = ALUOut BR 0 3 PC = { PC[31:28], IR[26:0], 2’b0} JMP 0 4

22 2/26/03Lecture 9 - ASM Diagrams22 About Lab 5 - Serial Receiver F clk = 16X BAUD RATE

23 2/26/03Lecture 9 - ASM Diagrams23 Lab 5 Design  Design circuit as a datapath / controller system  General Approach: 1.Wait for the falling edge of the START bit. 2.Delay to the center of the START bit and sample the current data value. If the data value is not still asserted low, ignore the START bit and return to step 1. 3.Delay to the center of the next data bit. Sample the value of the data value and shift it into a shift register. 4.Repeat step 3 seven more times. 5.Delay to the center of the stop bit and sample. If the value is not correct, indicate a framing error condition. 6.Indicate that valid data is available in the shift register. 7.Go back to step 1.

24 2/26/03Lecture 9 - ASM Diagrams24 Coming Up:  Multiple Controller / Datapath Designs  Synchronization Issues with Multiple Controllers

25 2/26/03Lecture 9 - ASM Diagrams25 Verification Plan  Definition: A Specification of the Verification Effort  Prerequisite: Specification document for design  Defnining Success - Must Identify  Features which must be exercisedunder which conditions  Expected Response

26 2/26/03Lecture 9 - ASM Diagrams26 Levels of Verification  Board  System / Subsystem  ASIC / FPGA  Unit / Subunit

27 2/26/03Lecture 9 - ASM Diagrams27 Levels of Verification  Connectivity  Transaction / Cooperative Data Flow  Functionality  Ad Hoc  Designer verifies basic functionality

28 2/26/03Lecture 9 - ASM Diagrams28 Levels of Verification - Notes  Stable interfaces required at each level of granularity

29 2/26/03Lecture 9 - ASM Diagrams29 System Design Issues  ASM Diagrams  Synchronization & Metastability  Handshaking  Working with Multiple Clocks

30 2/26/03Lecture 9 - ASM Diagrams30

31 2/26/03Lecture 9 - ASM Diagrams31

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