1. Issues in Future NoC Ran Ginosar

2. 2 Research Directions – Now NOC for CMP for ASIC / SOC / MPSoC for All Physical Flow CTL Architecture Routing Photonic, RF, Wireless Is this NOC research? or, Is this CMP / Many-core research? Will you submit here or go to ISCA? HPCA? Custom everything Non-Uniform Power, latency, throughput, reliability, cost Uniform Processor to processor, or proc. to mem. Mesh, MIN Caches

3. Ran Ginosar 3 to mesh or not to mesh Mesh—default topology –Possibly with shortcuts, with serial b’cast –Does it make programming easier?  But failed in large parallel processors –As did its n-dim version, the (k-ary) hypercube Alternative: Shared mem non-cached MIN –Cf. Cray cylinder and 1930-1970 phone + mpp research P M P M P M P M P M P M P M P M P M P M P M P M PPP M M M M PP PPPPP M M M M M M M M M M

4. Ran Ginosar 4 Power Model (and how it affects the NoC) Fixed chip area More processors  smaller processors

5. Ran Ginosar 5 Power Model (and how it affects the NoC) power  1/  N perf   N freq  1/  N Perf / power  N 64 2561K4K

6. Ran Ginosar 6 The challenge More processors achieve higher performance and lower power But more processors challenge the NoC –Hard to create –Hard to provide throughput –Hard to contain latency –Hard to cache Locality breaks P-M distances highly skewed

7. Ran Ginosar 7 The future of NoC research If this research succeeds, it will disappear But we won’t let it