1. Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

2. Comparator 2014Digital Integrated Circuits - week seven2

3. Elementary comparator 2014Digital Integrated Circuits - week seven3

4. Log-depth comparator 2014Digital Integrated Circuits - week seven4

5. Complex (random) circuits An universal circuit: 2014Digital Integrated Circuits - week seven5 Size  O(2 n ) Depth  O(n)

6. 2014Digital Integrated Circuits - week seven6

7. 2014Digital Integrated Circuits - week seven7 S EMUX = 6 S 3U_circuit = 42

8. 2014Digital Integrated Circuits - week seven8 S 3InMajority = 12

9. Many-input random circuit 2014Digital Integrated Circuits - week seven9

10. 2014Digital Integrated Circuits - week seven10

11. 2014Digital Integrated Circuits - week seven11

12. Applying the de Morgan theorem results a Read-Only Memory (ROM) which is not a memory, it is a combinational circuit implemented as a Look-Up Table (LUT). x n-1, x n-2, … x 0 : is the “address” f, g, … s : is the “content stored at” x n-1, x n-2, … x 0 2014Digital Integrated Circuits - week seven12

13. First-order – 1-loop digital systems Elementary latch Clocked latch Master-slave flip flop: serial extension Random Access Memory (RAM): parallel extension Register: serial-parallel extension 2014Digital Integrated Circuits - week seven13

14. Stable – unstable loops 2014Digital Integrated Circuits - week seven14

15. Low-cost oscillator 2014Digital Integrated Circuits - week seven15

16. 2014Digital Integrated Circuits - week seven16

17. Serial composition: serial shift register 2014Digital Integrated Circuits - week seven17

18. Parallel composition: Random Access Memory (RAM) 2014Digital Integrated Circuits - week seven18

19. 2014Digital Integrated Circuits - week seven19

20. Expanding the number of bits 2014Digital Integrated Circuits - week seven20

21. Expanding the number of words 2014Digital Integrated Circuits - week seven21

22. Synchronous RAM 2014Digital Integrated Circuits - week seven22

23. For L < 130 nm writing is synchronous, while reading could be synchronous or asynchronous 2014Digital Integrated Circuits - week seven23 Example of synchronous reading:

24. Register file 2014Digital Integrated Circuits - week seven24

25. 2014Digital Integrated Circuits - week seven25 Reading is asynchronous

26. Home work 7 Problem 1: Let be the log-depth comparator (see slide 4) with n = 8. Compute de size of the circuit (the number of inputs in all inverting circuits). Problem 2: Design, using the method presented in the slide no. 7, the circuit whose “program” is 11100100. Compute the final size (the number of inputs in all inverting circuits). Problem 3: Let be the low cost oscillator form the slide 16. Its output is connected to the input of an inverter. 1. Compute the frequency of the signal generated, f osc, when: For the NAND gate: t pLH = 40ps, t pHL = 60ps For the first NOT (connected to the NAND’s output): t pLH = 50ps, t pHL = 30ps For the second NOT: t pLH = 100ps, t pHL = 60ps 2. What will be f osc if the output of the same oscillator will be connected to the input of two invertors instead of one? 2014Digital Integrated Circuits - week seven26