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CSE111: Great Ideas in Computer Science Dr. Carl Alphonce 219 Bell Hall Office hours: M-F 11:00-11:50 645-4739

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Presentation on theme: "CSE111: Great Ideas in Computer Science Dr. Carl Alphonce 219 Bell Hall Office hours: M-F 11:00-11:50 645-4739"— Presentation transcript:

1 CSE111: Great Ideas in Computer Science Dr. Carl Alphonce 219 Bell Hall Office hours: M-F 11:00-11:50 645-4739 alphonce@buffalo.edu

2 Announcements Recitations have started this week! You have this week and next to complete HW1. 2

3 COMMUNICATION students 3

4 cell phones off (please) 4

5 Agenda Review from last class –two’s complement –underlying hardware Today’s topics –various circuits 5

6 AND gate 6 ABY 000 010 100 111

7 OR gate 7 ABY 000 011 101 111

8 NOT gate 8 AY 01 10

9 physical vs. logical perspectives Physical reality: Logical view: WIRE Carries a HIGH voltage or a LOW voltage WIRE Carries a 1 or a 0 9

10 Idea 10

11 Controlling flow 0 11

12 Controlling flow 1 12

13 Two in a row? 0 13

14 AND gate For which input values is output 1? For which input values is output 0? Inputs are on left Output is on right 14

15 OR gate For which input values is output 1? For which input values is output 0? Inputs are on left Output is on right 15

16 NOT gate For which input value is output 1? For which input value is output 0? Input is on left Output is on right 16

17 Flip-flop (a bit of memory!) S (set) R (reset) remembered value 17

18 Setting the flip-flop The normal value of R and S is zero. S (set) = 0 R (reset) = 0 remembered value 18

19 Setting the flip-flop To store 1 in the flip-flop, we “raise” S to 1… S (set) = 1 R (reset) = 0 remembered value 19

20 Setting the flip-flop …which makes the output of the OR gate 1. S (set) = 1 R (reset) = 0 remembered value 20 1

21 Setting the flip-flop The NOT gate inverts this 1 value to 0, which becomes the second input to the upper OR gate. S (set) = 1 R (reset) = 0 remembered value 21 10 0

22 Setting the flip-flop Since both inputs of the upper OR gate are zero, its output is zero. S (set) = 1 R (reset) = 0 remembered value 22 1 0 0 0

23 Setting the flip-flop The NOT gate inverts this 0 to a 1; this value becomes the second input to the bottom OR. S (set) = 1 R (reset) = 0 remembered value 23 1 0 0 0 1 1

24 Setting the flip-flop Because the output of the bottom OR gate will now stay at 1, we can lower S to zero, and the circuit will stay in a stable state, with 1 as the remembered value! 24 Resetting the flip-flop Resetting the remembered value to zero is similar, except we raise, then lower, the value on R. S (set) = 0 R (reset) = 0 remembered value 1 0 0 0 1 1

25 One-bit Half Adder 25 A B S C

26 One-bit Full Adder 26 A B CoutCout S CinCin


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