1. 1 CS294 Project VIRAM-1 Verification Retreat – Winter 2001 Sam Williams

2. 2 CS294 Project Current Debug / Verification Efforts Current m5kc+fpu :program simulation on RTL m5kc+vu+xbar+dram :program simulation on RTL AU : corner cases + random values on VERILOG netlist To Do Entire VIRAM-1 :program simulation on RTL (m5kc+vu+fpu+xbar+dram) Vector Register File : only a few cases have been (layout) spiced.

3. 3 CS294 Project Verify script Command line args include mode, and switches for disabling state initialization, method for init/test, run from on/off chip, turn of TLB, etc… Implemented a trace comparator capable of handling out of order commit, and partial execution few issues need to be hammered out for vu trace generation Tests can fail for self-check (software), unexpected exceptions, simulator failure, traces not consistent, etc… Since there are currently two different processors being verified, each had to have its own verify script and random test generator..test.r vsim simv.s rand_gen Insert init, self-check, c, etc… pass / fail verify.execute.pl Trace compare Command line args

4. 4 CS294 Project Progress vsim m5kc+vu+ xbar+dram m5kc+fpu m5kc ISAXC’s Arith.  KernelsTLB  Kernels randomcompiled MIPS Testsuite ISAXC’s Arith.  KernelsTLB  Kernels randomcompiled ISA XC’s Arith.  Kernels randomcompiled Testsuite on Synthesized VIRAM-1 (superset of above) Entire VIRAM-1 Testsuite Testsuite on Synthesized MIPS testsuite is about 1700 test-mode combinations + <100 FP tests-mode combinations that are valid for the VIRAM-1 FPU Additionally, entire VIRAM-1 testsuite has about 2200 tests, each of which can be run in 200 modes (only 1 mode has been run). Each mode is 24M instructions, and 4M lines of asm code Vector unit currently passes about 1800 tests (only the ISA sub suite) There are about 200 exception tests for both coprocessors Kernel tests are long, but there are only about 100 of them Tests are continually being written, so that they are ready once the RTL can run them MIPS Vector Subset of VIRAM-1 Testsuite FPU Subset of VIRAM-1 Testsuite + MIPS FPU Testsuite Entire VIRAM-1 Testsuite

5. 5 CS294 Project Test File Format Retrospective init/test functions aren’t written by the test writter, this allowed them to be switched as needed. e.g. when vld/vst weren’t working, vector register init/test was handled via vins/vext. The test was identical, all that changed was a command line option. xbar had a bug in it which prevented any access to DRAM (from m5kc or vu). Another command line allowed running tests from off chip memory, and forced application of the previous option Test format allows for easy modification to reduce simulation time in a debug cycle. Difficult to apply ISA changes to the entire test suite. e.g. half as many registers, changes in functionality for instructions, narrow element ordering, etc… [INIT] vr:0 half 0x7fff 0x0001 0xffff 0x7fff 0x0001 0xffff 0x7fff 0x0001 0xffff vr:1 half 0x7fff 0x7fff 0x7fff 0x0001 0x0001 0x0001 0xffff 0xffff 0xffff [CODE] li a0,1 ; vcset a0,vpw li a0,9 ; vcset a0,vl vfclr $vf8 ; vfset vfmask0 vadd.vv $vr2,$vr1,$vr0 vfor.sv $vf16,$vs0,$vf8 END [TEST] vr:2 half 0xfffe 0x8000 0x7ffe 0x8000 0x0002 0x0000 0x7ffe 0x0000 0xfffe vf:16 hex1 d0000000000000000000000000000000

6. 6 CS294 Project Bug Trends xbar/DRAM/SysAD timing and arbitration problems VERILOG could use extensions for handling control logic for multiple lanes instead of copying and modifying code, which led to many typos Major mistake in xbar functionality had to be fixed with major memory pipeline change. A few chaining errors so far Tests which had hand coded versions of boot code were not kept sync’d with master version (e.g. some regs had to be initialized, and were in master version, but not in the handful of tests which had their own version) ISA docs were not kept in sync with RTL, as a result many tests which look correct failed on RTL. (vector processing instructions, lack of interlocks) FP execution unit as it was shipped to us had many flaws with respect to exceptions and NaN’s – fixed to make it IEEE compliant FP reorder buffer / CDB problems missing results cop0 hazards initially weren’t reported by vsim, and caused hard fails on RTL Instruction Encoding – some instructions were encoded differently in the RTL than what had been used by the assembler / software simulator

7. 7 CS294 Project VIRAM-1 Board Daughter card (modified m5kc core card) has DIMM, VIRAM-1, and chipset (which maps SysAD  PCI,SDRAM) Yamon software can be used to directly download and run programs to daughter card via ethernet or serial. An m5kc based core card will allow us to run thru the methodology before receiving parts. Atlas board has PCI, compact PCI, SCSI, Parallel, Ethernet, KB/Mouse, USB, Serial devices. Will allow for creation of VIRAM- 1 workstation For OS support, we would have to modify an unsupported MIPS Linux port. The vector unit can only touch on chip memory. viram1chipset Daughter card Atlas board

8. 8 CS294 Project Still Left To Do FPU RTL almost done, needs a little more work. VU RTL verification needs to be completed, only done with ISA Integrate everything together for VIRAM-1 RTL model Include real versions of AU, xbar, VRF Iterate over timing driven layout, to ensure nothing is broken Board/daughter card checks Linux/MIPS port to Linux/VIRAM-1