1. Aiman El-Maleh, Ali Alsuwaiyan King Fahd University of Petroleum & Minerals, Dept. of Computer Eng., Saudi Arabia Aiman El-Maleh, Ali Alsuwaiyan King Fahd University of Petroleum & Minerals, Dept. of Computer Eng., Saudi Arabia An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits

2. 2 OutlineOutline n Introduction n Problem definition n Illustrative example n Proposed relaxation algorithm n Experimental results n Improving the effectiveness of test compaction & compression n Conclusion n Introduction n Problem definition n Illustrative example n Proposed relaxation algorithm n Experimental results n Improving the effectiveness of test compaction & compression n Conclusion

3. 3 IntroductionIntroduction n With today’s technology, complete systems with millions of transistors are built on a single chip. n Increasing complexity of systems-on-a-chip and its test data size increased cost of testing. n Test data must be stored in tester memory and transferred from tester to chip. n Cost of automatic test equipment increases with increase in speed, channel capacity, and memory. n Need for test data reduction is imperative. Test compaction. Test compaction. Test compression. Test compression. n With today’s technology, complete systems with millions of transistors are built on a single chip. n Increasing complexity of systems-on-a-chip and its test data size increased cost of testing. n Test data must be stored in tester memory and transferred from tester to chip. n Cost of automatic test equipment increases with increase in speed, channel capacity, and memory. n Need for test data reduction is imperative. Test compaction. Test compaction. Test compression. Test compression.

4. 4 IntroductionIntroduction n Effectiveness of test compaction and compression techniques can improve significantly if a partially specified (relaxed) test set is provided. n Most compression techniques assume a relaxed test. n Compaction achieved by test vector merging of compatible vectors. n Test relaxation can improve effectiveness of dynamic test compaction by taking advantage of random test pattern generation. n Test relaxation can also help in test power reduction Specify relaxed bits to reduce number of transitions during scan. Specify relaxed bits to reduce number of transitions during scan. n Effectiveness of test compaction and compression techniques can improve significantly if a partially specified (relaxed) test set is provided. n Most compression techniques assume a relaxed test. n Compaction achieved by test vector merging of compatible vectors. n Test relaxation can improve effectiveness of dynamic test compaction by taking advantage of random test pattern generation. n Test relaxation can also help in test power reduction Specify relaxed bits to reduce number of transitions during scan. Specify relaxed bits to reduce number of transitions during scan.

5. 5 Problem Definition n Given a test set of a given combinational or full-scan circuit, generate a partially specified test set that maintains the same fault coverage while maximizing the number of unspecified bits i.e., Xs. n Test relaxation problem has not been solved effectively in literature. n A test set can be relaxed using a brute-force method Every bit is tested for possibility of changing it to x by fault simulation. Every bit is tested for possibility of changing it to x by fault simulation. Impractical for large circuits. Impractical for large circuits. n Dynamic compaction does not relax an already existing test set. n Given a test set of a given combinational or full-scan circuit, generate a partially specified test set that maintains the same fault coverage while maximizing the number of unspecified bits i.e., Xs. n Test relaxation problem has not been solved effectively in literature. n A test set can be relaxed using a brute-force method Every bit is tested for possibility of changing it to x by fault simulation. Every bit is tested for possibility of changing it to x by fault simulation. Impractical for large circuits. Impractical for large circuits. n Dynamic compaction does not relax an already existing test set.

6. 6 Thus, to guarantee fault detection, G1=0 implies A=0 (Because A is unreachable). Illustrative Example G3 G1 G5 G6 G2 G4 0 0 0 0 0 0 1 1 1 0 0 A B C D E 0/1 1/0 0/1 0/1 1/0 1/0 0 Fault excitation Fault propagation B=0 satisfied Apparently, G1=0 satisfied and thus A=X (WRONG!!) G3=0 implies C=0, DE=XX OR C=X, DE=00 0 0/00/x x 1/x To guarantee stem faults propagation, never justify a controlling value from a reachable line. From this example, we conclude that we need to identify reachable lines before justification. B stuck-at-1

7. 7 Proposed Technique For every test vector t do Fault simulate the circuit under the test t For every newly detected fault f do BuildRequirementList( f ) /**** Returns L ****/ For every line j in L do justify( j ) End for Mark all lines as unreachable End for Output relaxed vector Mark all lines as non-required End for For every test vector t do Fault simulate the circuit under the test t For every newly detected fault f do BuildRequirementList( f ) /**** Returns L ****/ For every line j in L do justify( j ) End for Mark all lines as unreachable End for Output relaxed vector Mark all lines as non-required End for

8. 8 Proposed Technique n Definition: A line l is said to be reachable from a stem s if the fault effect in stem s reaches line l. n BuildRequirementList ( f ): Assume the faulty line is j. Assume the faulty line is j. Adds j to L (fault activation). Adds j to L (fault activation). Trace j forward until a fanout stem s is reached and add all side inputs of traced path to L. Trace j forward until a fanout stem s is reached and add all side inputs of traced path to L. Mark reachable lines from s until an output is reached. Mark reachable lines from s until an output is reached. Trace backward from the reached output to the stem and add all side inputs of reachable lines to L. Trace backward from the reached output to the stem and add all side inputs of reachable lines to L. n Definition: A line l is said to be reachable from a stem s if the fault effect in stem s reaches line l. n BuildRequirementList ( f ): Assume the faulty line is j. Assume the faulty line is j. Adds j to L (fault activation). Adds j to L (fault activation). Trace j forward until a fanout stem s is reached and add all side inputs of traced path to L. Trace j forward until a fanout stem s is reached and add all side inputs of traced path to L. Mark reachable lines from s until an output is reached. Mark reachable lines from s until an output is reached. Trace backward from the reached output to the stem and add all side inputs of reachable lines to L. Trace backward from the reached output to the stem and add all side inputs of reachable lines to L.

9. 9 Proposed Technique n Justification of a line J, justify( J ): CaseAction J is a NOT, XOR, XNOR Justify all inputs of J J has a non-cont. value Justify all inputs of J There is an unreachable input K with cont. value Justify K Otherwise Justify all inputs of J

10. 10 Selection Criteria n Justification of a controlling value may involve some selection. n Cost functions are employed to minimize the number of specified inputs. n Regular cost functions used in ATPG can b e used don’t take advantage of the fact that a stem can justify several required values. don’t take advantage of the fact that a stem can justify several required values. n Fanout-based cost functions are proposed to take advantage of this fact. n Justification of a controlling value may involve some selection. n Cost functions are employed to minimize the number of specified inputs. n Regular cost functions used in ATPG can b e used don’t take advantage of the fact that a stem can justify several required values. don’t take advantage of the fact that a stem can justify several required values. n Fanout-based cost functions are proposed to take advantage of this fact.

11. 11 Selection Criteria n For an AND gate, fanout-based cost functions are computed as follows: Let l be the output of AND gate with i inputs. Let l be the output of AND gate with i inputs. Let F(l) denote the the fanout (i.e. the number of fanout branches) of line l. Let F(l) denote the the fanout (i.e. the number of fanout branches) of line l. 0-controllability of line l: 0-controllability of line l: 1-controllability of line l: 1-controllability of line l: n For an AND gate, fanout-based cost functions are computed as follows: Let l be the output of AND gate with i inputs. Let l be the output of AND gate with i inputs. Let F(l) denote the the fanout (i.e. the number of fanout branches) of line l. Let F(l) denote the the fanout (i.e. the number of fanout branches) of line l. 0-controllability of line l: 0-controllability of line l: 1-controllability of line l: 1-controllability of line l:

12. 12 Selection Criteria - Example RC 0 (G4)=2 FC 0 (G4)=2 To detect fault A s-a-0 value G5=0 is required RC 0 (G3)=2 FC 0 (G3)=1 RC 0 (C)=1 FC 0 (C)=1/2 RC 0 (G1)=1 FC 0 (G1)=1/2 RC 0 (G2)=1 FC 0 (G2)=1/2 Based on regular cost functions, either G3 or G4 could be selected, which may result in two required values. result in two required values. Based on fanout-based cost functions, G3 will be selected, which results in one required value C=0. To justify G5=0, either G3=0 or G4=0 could be selected.

13. 13 Selection Criteria n In general, fanout-based cost functions provide better selection criteria than regular cost functions. n There are situations where regular cost functions provide better selection criteria. n To take advantage of both, a weighted selection criteria is used n In general, fanout-based cost functions provide better selection criteria than regular cost functions. n There are situations where regular cost functions provide better selection criteria. n To take advantage of both, a weighted selection criteria is used

14. 14 Experimental Results n ISCAS 85 and full-scan versions of ISCAS 89. n SUN Ultra60, 450 MHZ, RAM=512 MB. n Used test sets are highly compacted and are generated by MinTest [Hamzaoglu et al., ICCAD 98]. n Compare our results with a brute-force relaxation method. n Effect of selection criteria on test relaxation. n Impact of test relaxation on test data compression based on FDR codes [Chandra et al., VTS 2001]. n Impact of test relaxation on test compaction by vector merging. n ISCAS 85 and full-scan versions of ISCAS 89. n SUN Ultra60, 450 MHZ, RAM=512 MB. n Used test sets are highly compacted and are generated by MinTest [Hamzaoglu et al., ICCAD 98]. n Compare our results with a brute-force relaxation method. n Effect of selection criteria on test relaxation. n Impact of test relaxation on test data compression based on FDR codes [Chandra et al., VTS 2001]. n Impact of test relaxation on test compaction by vector merging.

15. 15 Percentage of Xs n Average Xs = 68.3% (brute-force). n Average Xs = 65.4% (proposed). n An average difference of only 2.9%.

16. 16 Test Relaxation CPU Time n Average CPU Time = 152725 Seconds (brute-force). n Average CPU Time = 6 Seconds (proposed).

17. 17 Cost Function Effect on Extracted Percentage of Xs Circuit A=0 B=0 A=1 B=0 A=0 B=1 A=1 B=1 A=1 B=2 A=1 B=6 c531548.52750.07652.06552.08052.08052.080 c755248.09148.32952.06852.07552.07552.075 c267065.89966.40768.37768.74868.74868.767 s537868.42269.89171.05770.48470.48470.753 S9234.163.62164.37265.94966.04666.04666.408 S15850.177.69377.85578.97178.39178.44878.830 S13207.192.45792.48592.92092.92092.92592.928 S38584.175.32875.83978.07277.79477.79577.951 s3841765.51865.86566.46766.16266.16466.171 s3593222.98628.12027.41528.23828.23828.238 Average62.85463.92465.33665.29465.30065.420

18. 18 Impact of Test Relaxation on FDR Compression

19. 19 Impact of Test Relaxation on Compaction by Vector Merging

20. 20 ConclusionConclusion n A novel and efficient test relaxation technique has been presented. n New selection cost functions proposed to maximize number of Xs. n While achieving slightly less test relaxation quality than brute-force test relaxation, the technique is faster by several orders of magnitude. n Demonstrated the impact of test relaxation in improving the effectiveness of test compaction and compression techniques. n A novel and efficient test relaxation technique has been presented. n New selection cost functions proposed to maximize number of Xs. n While achieving slightly less test relaxation quality than brute-force test relaxation, the technique is faster by several orders of magnitude. n Demonstrated the impact of test relaxation in improving the effectiveness of test compaction and compression techniques.