1. Digital Alarm System Experiment 9

2. Experiment 8: What You May Have Missed Continued use of structural modelingContinued use of structural modeling VHDL behavioral modelsVHDL behavioral models –Best approach for sequential circuits VHDL model for memoryVHDL model for memory –D and T flip-flops –Synchronous and asynchronous control More complex circuitry creationMore complex circuitry creation –less boring than the usual stuff

3. Experiment 8: Questions 1.How would you implement a T flip-flop using a D flip-flop and some additional logic gates? Draw the circuit for this in your report. 2.What were the operational characteristics of the circuit used in Procedure 2. In other words, completely describe the operation 4-bit counter used in this procedure. 3.What output is displayed when the count value is greater than nine? Why is this? Is this a problem? 4.What were the operational characteristics of the circuit used in Procedure 3. In other words, completely describe the operation of the circuit used in this procedure.

4. Experiment 8: Random Notes Timing diagrams need to be annotatedTiming diagrams need to be annotated –it’s not the reader’s job to figure out what is going on or what is important Don’t forget circuit diagramsDon’t forget circuit diagrams –circuits you designed/experimented with –answers to questions Take more space: use blank lines in code and in experiment write-upTake more space: use blank lines in code and in experiment write-up Lab reports:Lab reports: –Ask yourself what is good and make you lab reports look that way –You should rarely ask yourself what the instructor wants

5. Instructional Objectives: To use VHDL behavioral modeling in the design of a Finite State Machine (FSM)To use VHDL behavioral modeling in the design of a Finite State Machine (FSM) To combine previously designed VHDL modules into a complete digital alarm systemTo combine previously designed VHDL modules into a complete digital alarm system

6. Sequential Storage Elements Storage elements in digital logic are sequential components whose output(s) are a function of both the current state and current input(s).

7. Finite State Machine A Finite State Machine (FSM) is a digital circuit whose state changes based on both the current state (of the FSM) and the current inputs The outputs of a FSM are functions of the current state (Moore Model) --or-- functions current state and current inputs (Mealy Model) Synchronous FSMs change their state with respect to a clock input and maintain their state (store their state) in flip- flops

8. FSM Models

11. Experiment 9 Overview P1:Finite State Machine Design 1.Design 2.Implement 3.Test P2:Digital Alarm System Combine earlier modules into a working system

12. State Transition Diagram UNARMED ALARM alarm ARMED armed State Output Legend Inputs OFF/ON=1 OFF/ON=0, BREAKIN=1 OFF/ON=1 OFF/ON=0

13. Present State Next State Table Present State Present Input Next State Present Output Q1 Q0 OFF/ON BREAKIN Q1* Q0* armed alarm 0 000 0 001 0 010 0 011 0 1.. 0 1 1 0 1 When your PS/NS Table is complete, obtain next state equations for Q1* and Q0* as functions of the current state (Q1 and Q0) and the current input (OFF/ON, BREAKIN) using a K-map. Equations for the output can be obtained by inspection.

14. FSM in VHDL ARCHITECTURE mysolution OF myFSM IS SIGNAL Q1, Q0: STD_LOGIC; BEGIN PROCESS (clk,Q1, Q0, offon, breakin ) BEGIN IF (rising_edge(clk)) THEN Q1 <= next state equation for Q1; Q0 <= next state equation for Q0; END PROCESS; alarm <= output equation for alarm signal; armed <= outputequation for armed signal; END mysolution;