1. Procedural Circuit Simulation with decida Richard V. H. Booth Agere Systems, Allentown, PA

2. 2 decida Device and Circuit Data AnalysisDevice and Circuit Data Analysis http://decida.orghttp://decida.org Platform for Procedural Circuit SimulationPlatform for Procedural Circuit Simulation M.S. Toth and R.V. Booth, “A Designer-Customizable Design Environment for Analog/Mixed-Signal Circuit Design,” presented at the 2001 O’Reilly Open-Source Convention, San Diego CA, July 2001.M.S. Toth and R.V. Booth, “A Designer-Customizable Design Environment for Analog/Mixed-Signal Circuit Design,” presented at the 2001 O’Reilly Open-Source Convention, San Diego CA, July 2001. http://conferences.oreillynet.com/cs/os2001/view/e_sess/1351http://conferences.oreillynet.com/cs/os2001/view/e_sess/1351 Compact Model Compiler (AMC)Compact Model Compiler (AMC) R.V.H. Booth, “An Extensible Compact Model Description Language and Compiler,” presented at the 2001 International Behavioral Modeling and Simulation Workshop, Santa Rosa CA, October 2001.R.V.H. Booth, “An Extensible Compact Model Description Language and Compiler,” presented at the 2001 International Behavioral Modeling and Simulation Workshop, Santa Rosa CA, October 2001. http://www.bmas-conf.org/web-docs/Repository/y2001/FinalPapers/Pdf/Booth.pdfhttp://www.bmas-conf.org/web-docs/Repository/y2001/FinalPapers/Pdf/Booth.pdf Device Measurements and Parameter ExtractionDevice Measurements and Parameter Extraction Data Analysis and VisualizationData Analysis and Visualization

3. 3 decida procedural simulation

4. 4 Procedural simulation Design phasesDesign phases Initial circuit module designsInitial circuit module designs Circuit module optimizationsCircuit module optimizations Pre-layout/post-layout characterizationsPre-layout/post-layout characterizations Model-building for high-level verificationModel-building for high-level verification Top-level simulations (pre-release/field)Top-level simulations (pre-release/field) Procedural simulationProcedural simulation Organized simulation runs/post-processing/bookkeepingOrganized simulation runs/post-processing/bookkeeping Can be used with ALL design phasesCan be used with ALL design phases

5. 5 Procedural Simulation Advantages of Procedural Simulation ApproachAdvantages of Procedural Simulation Approach All variations over processing, supply voltage, operating temperature, control register/divider settings can be performedAll variations over processing, supply voltage, operating temperature, control register/divider settings can be performed Simulation results are post-processed in-line, and can be evaluated before the entire range of variations are doneSimulation results are post-processed in-line, and can be evaluated before the entire range of variations are done Simulations can be farmed out to compute farmSimulations can be farmed out to compute farm Script is ready for simulations with post-layout netlists or revised process filesScript is ready for simulations with post-layout netlists or revised process files Simulation approach is exactly documentedSimulation approach is exactly documented Scripts can be re-used for similar modulesScripts can be re-used for similar modules Simulator independenceSimulator independence

6. 6 PLL design component tests PFD charge-pump REF FBK UP DN VCO loop filter feedback divider OUT bias regulator VREF IREF VREG DIV VC

7. 7 PLL design component tests PFD charge-pump REF FBK UP DN VCO loop filter feedback divider OUT bias regulator VREF IREF VREG DIV VC dc analysis (T, Vdd) stability line-rejection load-rejection startup dropout compact model

8. 8 PLL design component tests PFD charge-pump REF FBK UP DN VCO loop filter feedback divider OUT bias regulator VREF IREF VREG DIV VC frequency versus VC jitter analysis range design gain design operating current powerdown current compact model

9. 9 PLL design component tests PFD charge-pump REF FBK UP DN VCO loop filter feedback divider OUT bias regulator VREF IREF VREG DIV VC locking time stability analysis phase/frequency hit operating current powerdown current compact model

10. 10 Open Source How do you develop a procedural circuit simulation platform while doing real work? Using the tool immediately for real work can make it exactly the right solution for the problem at hand. But:Using the tool immediately for real work can make it exactly the right solution for the problem at hand. But: the solutions must be generalized appropriatelythe solutions must be generalized appropriately infrastructure specifics promote hackinginfrastructure specifics promote hacking Most people do it (shell scripts, etc.)Most people do it (shell scripts, etc.) If it’s just one person using the platform, then updating it doesn’t make anyone angry. But if more than one (a few):If it’s just one person using the platform, then updating it doesn’t make anyone angry. But if more than one (a few): extensibility and incremental development doesn’t require major code releases, just feature-addingextensibility and incremental development doesn’t require major code releases, just feature-adding spin-off tools can be used by othersspin-off tools can be used by others Open Source!Open Source! customers can use itcustomers can use it tool becomes more generaltool becomes more general tool benefits from real code development expertisetool benefits from real code development expertise

11. 11 decida architecture Tcl/Tk decida BLT [incr tcl] Application decida library package libraries user libraries simulators

12. 12 decida architecture Tcl/Tk decida BLT [incr tcl] Application decida library package libraries user libraries simulators Tcl/Tk Core

13. 13 decida architecture Tcl/Tk decida BLT [incr tcl] Application decida library package libraries user libraries simulators Extensibility

14. 14 decida architecture Tcl/Tk decida BLT [incr tcl] Application decida library package libraries user libraries simulators Natural Development Flow

15. 15 decida extension Data object data dat1 dat1 read vco.prelayout.out dat1 plot Time Vco dat1 jitter Vco

16. 16 decida extension Circuit Simulator Object celerity sim1 sim1 command “.rd vco10v3.sp” sim1 command “.dc vcont 0 $vdd.1” sim1 info elements

17. 17 decida extension Test Bench Object TestCkt tckt1 tckt1 embed vco10v3.sp tckt1 monitor V(OUT) set datq [tckt1 analysis_data.dc vcont 0 $vdd.1]

18. 18 decida extension Test Suite Object TestSuite ts1 ts1 add-test temp-sweep {...} {...} ts1 configure –simulator hspice ts1 go

19. 19 TestSuite Script example TestSuite ts1 –mode prelayout –simulator hspice \ -modeldir /home/models/lv090g/sim \ –netlistdir /home/mgb1/work/proj1 \ -vnom 3.3 –vlow 3.0 –vhigh 3.6 #----------------------------------------------------- # test definitions #----------------------------------------------------- ts1 go –gui exit 0

20. 20 TestSuite test menu

21. 21 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Specify a Test named “dc”

22. 22 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Specify list of netlists to embed

23. 23 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Specify list of node voltages and element currents to monitor

24. 24 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Create Report object to collect simulation results

25. 25 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Perform analysis for each Case combination (process/temperature/voltage)

26. 26 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Simulator-independent reference to Processing-case library

27. 27 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Loop over range of supply voltages (over-ride case-combination setting)

28. 28 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Simulator-independent power-supply setting

29. 29 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } Perform analysis and collect the results In an auxiliary data object

30. 30 Bandgap temperature sweep test ts1 add-test dc { prelayout {bgfra_test.sp bgfra.sp} postlayout {bgfrq_test.sp bgfra.extract.sp} } { tckt monitor {V(VBG) IBG=I(MN1) @XBGFRA: V(Q1E)} Report rpt $test.$mode.report –verbose 1 rpt header “Case Temp Vdd VBG IBG VQ1E” foreachcase {WCS WCF} { tckt setlibs $lib foreach vdd [range-sample $vlow $vhigh.1 –step] { tckt setsupply VDD $vdd set d [tckt analysis_data.dc temp -40 125 5] rpt report-data $d key TEMP vdd VBG IBG VQ1E $d delete } delete object rpt } No post-processing required: Dump the results to the report object

31. 31 dataview of test results

32. 32 Last Words analysis/visualizationanalysis/visualization dataviewdataview X-Y/histogram/smith-chartX-Y/histogram/smith-chart FFT/IFFTFFT/IFFT eye/scope diagramseye/scope diagrams jitter analysisjitter analysis signal analysissignal analysis simulator-independencesimulator-independence speed/accuracyspeed/accuracy pre-layout/post-layoutpre-layout/post-layout verificationverification convergenceconvergence

33. 33 decida Open-Source project http://decida.org executables for Solaris and Linux