1. LOGO HW/SW Co-Verification -- Mentor Graphics® Seamless CVE By: Getao Liang March, 2006

2. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Contents 1. HW/SW Co-Verification 2. Seamless CVE 3. CVE Tutorial 4. Conclusions

3. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Introduction  Embedded System & SoC  Hardware Processor (s) Memory Blocks IP Blocks Bus  Software Communication with CPU and I/O Memory Access  HW/SW Integration

4. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Traditional Design Cycle 1. High-Level Design 2. Detail & Implementation 3. Physical Integration Requirement Analysis Sub-systems High-Level Simulation HW/SW Interface Hardware Prototyping Hardware Design & Simulation Software Design HW/SW Integration

5. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Motivation  Time to Market  Shorten Time-to-Market = ? Save Resource More Profit Market Domination  Advance Verification  Lower Cost to Problem Correction  Easier Debugging

6. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Comparison

7. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 HW/SW Co-Verification Model

8. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Co-verification Vs. Simulation  RTL Simulation  Pure RTL models  Slow: <100Hz  Unable to address all debug requirement  Co-Verification  Orders of Magnitude Faster  Increased Comprehension  Support for Abstract Models

9. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Contents 1. HW/SW Co-Verification 2. Seamless CVE 3. CVE Tutorial 4. Conclusions

10. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Mentor Graphics ® Seamless CVE  Interactive Debugging Tool Bus Interface Model Memory Models

11. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Key Concepts of CVE  Accelerating Co-Verification Process  Separate Processor’s Functions  Suppress Bus Cycles Selectively  Important Components  Processor Support Packages (PSP) Instruction Set Model (ISM) - SW Bus-Interface Model - HW  Memory System Optimizable Memory Models Coherent Memory Server (CMS)  Coherent Timers

12. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Processor Support Packages

13. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Instruction Set Model Software Model Functional Behavior of Processor’s Instruction Set Abstract Model of Data Processing Instruction Set Simulation - IIS - Running ISM on a software simulator.

14. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Bus-Interface Model Hardware Model Input/Output Pin Behavior of Processor No Internal Logic of Processors Bus Activities R/W Memory R/W I/Os R-modify-W Reset and Halt.Interrupts, Faults Bus Request & Grant

15. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Software Co-Verification Introduce Seamless application into design flow, and load executable software modules into ISM address space of the processor. Design software with cross- language tools to generate machine code for target processor. The Seamless kernel handles communication s between the ISM and Bus- interface model in hardware part. SW Design LoadingTest

16. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Optimizable Memory Models Generic Optimizable Memory Models – Supplied with Seamless as HDL files. (for simple memory blocks, like dRAM, sRAM, DP- RAM, FIFO, Register Memory.) Denali Memory Models – Created with PureView application. (for commercial memory devices) Seamless HDL Memory Interface – Converted from existing models to Seamless optimizable models

17. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Optimizable Memory Models (Cont’l)  Generic Memory Models  $CVE_HOME/vsim_vdl  $CVE_HOME/vlog  Denali Memory Models  Obtain a SOMA file http://www.ememory.com  Generate HDL Memory Model PureView or MemMaker  HDL Memory Interface  Compile iram.vhd  Add USE work.cve_direct.all;  Modify with Seamless HDL memory interface calls cve_RegisterMemory() cve_ReadMemory() cve_WriteMemory()

18. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Optimization  Why  Accuracy vs. Performance  What  Frequently accessed memory  How  Direct Access (bus cycles hiding)  By Coherent Memory Server CMS

19. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Optimization Categories  Disables hardware bus cycles when accessing optimizable memory  Functional Accurate Cycle Accurate Data Access Optimization  Eliminates all bus activities for instruction fetches from optimizable memory  Functional Accurate Cycle Accurate Instruction Fetch Optimization Time Optimization  Decouples time synchronization between HW and SW  Functional Accurate

20. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Full Activity Simulation Simulation Bus Activity Instruction Fetch Memory Read/Write I/O Read/Write

21. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Optimized Simulation Simulation Bus Activity Instruction Fetch Memory Read/Write I/O Read/Write Memory Write to UN- OPTIMIZABLE Address

22. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Increased Performance

23. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Seamless Coherent Timers  Maintain an accurate count of clock cycles when running in time-optimized mode.  Be programmed to make logic simulator to service timer events appropriately.

24. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Contents 1. HW/SW Co-Verification 2. Seamless CVE 3. CVE Tutorial 4. Conclusions

25. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Basic Steps  Hardware Design  Replace processor modules with corresponding bus-interface Models  Modify memory modules  Software Design  Machine code for target processor  Software for Host Code Execution (HCE)  CVE Invocation  Logic and SW simulators configuration  Memory mapping

26. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Demo Design

27. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Demo Tutorial  Setup Environment  Compile Software  Invoke Seamless  Invoke Logic Simulator - ModelSim VHDL  Configure the Processor - DLX  Setup SW simulator/debugger – MDB  Map memory instances  Define memory access detail  Start Co-verification Session  Enable Data Access Optimization  Enable Time Optimization  Enable Instruction Fetch Optimization

28. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Contents 1. HW/SW Co-Verification 2. Seamless CVE 3. CVE Tutorial 4. Conclusions

29. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 Conclusions  Early Integration  Shorten time-to-market  Lower cost for verification and correction  Easy Debugging  Control SW execution  View/Change memory contents  Enhancing Performance  ISM + BIM  CMS + Optimizable Memory

30. THE UNIVERSITY OF TENNESSEE ECE 652 Spring 2006 References  Mentor Graphics, Seamless Reference Manuals  Milan Saini, Co-Verification Enhances Time to Market Advantage of Platform FPGAs  Mike Andrews, Seamless-izing Memories for Seamless Hardware/Software  J. M. Ng, Enhancing HW/SW Co-Verification for Embedded System with Seamless  CIC brady@cic.org.tw, HW/SW Co-Verification using Mentor Graphics Seamless CVE: A Case Study with AUK system

31. LOGO Liang, Getao – gliang (at) utk (dot) edu