1. FRC FPGA Architecture Kickoff 2009

2. Agenda FRC Robot Controller Architecture FPGA Features and Use Cases Break WPILib for LabVIEW Break WPILib for C / C++

3. cRIO Architecture Freescale PowerPC Ethernet RS232PCIXilinx FPGASlot 1Slot2…Slot 8

4. NI 9201 Architecture 8 Channel Analog Input Module FPGAADCMUXChannel 1Channel 2… Channel 8 / Battery NI 9201

5. NI 9403 Architecture 32-Channel Bidirectional Digital I/O Module FPGANI Lightning Bug Pull-up Resistors Digital I/O (14) Tristate Buffer Hobby PWM Output (10) Shift RegisterRelay (8 x 2) Robot Signal Light I2C Header Outputs (4) Grounding FETs I 2 C Bus NI 9403 Digital Breakout

6. Digital Breakout Architecture NI 9403 Pull-up Resistors Digital I/O (14)

7. Digital Breakout Architecture NI 9403Tristate Buffer Hobby PWM Output (10)

8. Digital Breakout Architecture NI 9403SPI Shift Register Relay (8 x 2) Robot Signal Light I2C Header Outputs (4)

9. Digital Breakout Architecture NI 9403 Grounding FETs I 2 C Bus

10. NI 9472 Architecture FPGABuffer Solenoid Channel 1 Solenoid Channel 2 … Solenoid Channel 8 NI 9472

11. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

12. Analog Input Use Case Angle of a Potentiometer Distance of a Maxbotics Ultrasonic Sensor Acceleration of an Accelerometer Axis Any other Very Low Frequency Analog Signal

13. Analog Input 12-bit ADC with +/-10V Range Access Factory Calibration Variable-Length Scan List – 8 maximum – Repeat entries allowed Scan Rate – Per module basis (one ADC) – 2us per Conversion Minimum i.e. 500kS/s with single entry scan list

14. Analog Input Sources Raw Samples – 16-bit – Updated After Each Conversion Oversample / Average Engine Output – 32-bit Windowed Register Access – Most recent sample

15. Analog Input Library API

16. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

17. Oversample / Average Engine (OAE) Use Case Oversample – Higher Resolution Samples – Lower Sample Rate Average – Same Resolution Samples – Lower Sample Rate – More Stable Sample Values

18. Oversample / Average Engine (OAE) Specified in bits – B bits: 2 B == N Samples – 15 bits Each Maximum Oversample – Sums N O samples Average – Sums N A samples – Divide by N A Output changes after N O x N A Samples

19. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

20. Accumulator Use case Hardware Numerical Integration Gyro – Integrate: Angular Rate  Angle

21. Accumulator 64-bit Value / 32-bit Count 2 available – Hardwired to Slot 1, AI 1 and AI 2 OAE Output Center Value Deadband Value Reset to Zero

22. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

23. Analog Trigger Use case Reflective Sensor Encoder Interrupt at Pot Value Sin-Cos Signal to Quadrature Variable Reluctance Sensor Any Analog Signal to Digital

24. Analog Trigger Trigger Events From Analog Signal Specify Upper and Lower Limit Source Raw or OAE Trigger State – High when Above Upper Limit – Low when Below Lower Limit – Unchanged when Between Limits (Hysteresis) In Window – Voltage between Upper and Lower Limit

25. Analog Trigger

26. Analog Trigger – Hysteresis

27. Analog Trigger – Hysteresis (Too Noisy)

28. Analog Trigger - Rollover Detection Use case Count Rollovers (Rotations) – Continuous-Turn Potentiometers – Magnetic Absolute Encoder – Any Signal that Rolls Over

29. Analog Trigger - Rollover Detection Jump Over Window Floating – Large Change in Value Average-Rejection Filter – 3 Point Filter Pulse Output – Rising and Falling Pulses – Cannot Read via Register; Routable Only

30. Analog Trigger – Rollover Detection Rising Trigger

31. Analog Trigger – Rollover Detection Rising Trigger, Low-Pass Filtered

32. Average Rejection Filter Use case Averaging Inherent in Sampling Process Perform More Averaging After Sampling – Changes the Effective Sample Rate – Increases the Effect of the Filter Balance Effective Sample Rate – Too Fast, the Filter Has Too Little Effect – Too Slow, Trigger False Positives True Slope Needs at least One Sample In Window

33. Average Rejection Filter

34. Analog Trigger – Rollover Detection Rising Trigger, Average Rejection

35. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

36. Digital Input / Output Use case Digital Input – Limit Switches Digital Output – Jaguar Coast / Brake Control Pulse Generator – Ping Signal for Ultrasonic Sensors

37. Digital Input / Output 6.525us Per Sample Output Enable (Change) – 17us Delay for I/O on Both NI 9403 Modules Output Latch Configurable Before OE Output Pulse Generator – Invert Bits For Some Time Then Reset – 1.6ms Maximum

38. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

39. Slow Digital Output Use case Spike Relay Control Robot Signal Light – Controlled by Network Status Code – Not Available 4 Outputs on I 2 C Header – Any Custom Circuits that need More Outputs

40. Slow Digital Output SPI Output to Sidecar Shift Registers 320us Per Update Spike Relay Control – Gated by Watchdog Robot Signal Light 4 Outputs on I 2 C Header

41. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

42. Hobby PWM Output Use case Jaguar Motor Controller – 1x Period Multiplier – 5ms Update Victor Motor Controller – 2x Period Multiplier – 10ms Update Hobby Servo – 4x Period Multiplier – 20ms Update

43. Hobby PWM Output 8-bit Generator 0 == Disable Output 1 == 0.65ms High 128 == 1.5ms High 255 == 2.35ms High Period Multiplier – 1x, 2x, or 4x Gated by Watchdog

44. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

45. I 2 C Bus Use case Hitechnic NXT Compatible Sensors – Compass – 3 Axis Accelerometer – Gyro (No Hardware Integration) Devantech Sensors – SRF08 Ultrasonic Range Finder – Compass Any Other I 2 C Compliant Sensors

46. I 2 C Bus Address / Register / Data Transaction Format Independent Bus Per Module 7-Bit Addresses Only Write 1 Byte Per Transaction Read 1, 2, 3, or 4 Bytes Per Transaction Clock Skewing Only On Read Between Data Bytes Slave Acknowledge Ignored Interrupt on Done

47. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

48. Digital Input Filtering Use case Debounce Buttons Synchronize Digital Input Signals Filter Out High Frequency Noise

49. Digital Input Filtering 3 Filters Per Module Filter Assigned Per Channel Correlation Between Channels – Updates at End of Correlation Period – Unchanged if Input Changed During Period All Routed Digital Inputs Can Be Filtered

50. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

51. Solenoid Output Use case Control Pneumatic Solenoids Less Space Than 4 Spikes

52. Solenoid Output Pass-through Gated by Watchdog

53. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

54. Watchdog Use case Ensure That Critical Code Keeps Running Added Safety if Used Correctly Not Mandatory; Strongly Recommended Disable to Keep Motors Running At Breakpoint

55. Watchdog Disables Actuator Outputs Configurable Timeout Feed To Keep Alive Manual Kill – Disable Outputs Now Immortal Mode – Timeout and Manual Kill Ignored – Outputs Enabled

56. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

57. Counter / Timer 2 Types of Counters – Dedicated 4x Quadrature Decoders 4 Available – General Purpose Counters 8 Available Signed 31-bit Value Most Recent Direction Timer On Each Counter Output

58. Counter / Timer (cont) Routable Input Sources – Digital Input Filter – Analog Trigger Disable (Ignore Inputs) Software Reset Value to Zero External Reset Value to Zero Routable Input

59. Dedicated 4x Quadrature Decoder Use case Highest Resolution Dedicated Hardware Absolute Angle – External Reset as Index Input

60. Dedicated 4x Quadrature Decoder A and B Channel Routable Inputs Count for Each Transition of A or B Signal 4x More Precise

61. 1x, 2x Quadrature Decoding Counter Use case Used Up All 4x Decoding Counters Less Resolution Needed More Averaging of Encoder Speed – Fewer Timer Events Per Rotation

62. Up / Down Counter Use case Count Full Rotations of Rollover Sensors – Route Analog Trigger Rising and Falling Pulses Simple Counter – Disable the “Count Down” Channel

63. External Direction Counter Use case BaneBots Encoder Divider Kit Other Encoder Types

64. General Purpose Counter Counting Modes – 1x or 2x Quadrature Decoding “A” and “B” Inputs – Up / Down Counter “Count Up” and “Count Down” Inputs – External Direction “Count” and “Direction” Inputs Rising, Falling, or Both Edge Sensitivity

65. Semi-Period Timer Use case Echo Signal from Ultrasonic Range Sensor Duty-Cycle Measurement – If Period is Fixed, Measure High or Low Pulse – If Not, Hard to Get Consistent Sample

66. Pulse-Length Direction Counter Use case Allegro ATS651 Gear Tooth Sensor – Direction Information Encoded in Pulse Length – Provided in Kit in 2005 Black PCB RevNC

67. General Purpose Counter (cont) Special Modes – Semi-Period Primary Output is Timer Odd Counter Value Means Measurement In Progress Select High or Low Semi-Period Single Input Channel – Pulse-Length Direction Direction to Count Determined From Pulse-Length Select Pulse-Length Threshold Single Input Channel

68. Timer Use case Measure Speed Detect Motor Stall Time Events

69. Timer Time Between Counter Events – Event == Value Change Stall Detection Sample Averaging – Sliding Window – Up to 128 Samples

70. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

71. SPI Engine Use case Interface Custom Circuits Some Sensors

72. SPI Engine Serial Peripheral Interface / Synchronous Serial Input and Output FIFOs – 512 Words Each Highly Configurable – Chip Select / Pre- or Post-Latch – Clock Polarity – Word Size (1-bit to 32-bit) – MSb or LSb First Streaming Interrupts – Receive Buffer Not Empty; Half Full – Transmit Buffer Half Empty; Empty and Idle

73. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

74. Time / Alarm Use case Time – Consistent us Value Across Subsystems – Fast, Precise Benchmark Source Alarm – Interrupt Based Task Scheduling (for C++)

75. Time / Alarm Time – 1us Resolution – 32-bit range (71.5 Minutes) Alarm – Schedule for a Specific Time – Generate an Interrupt – Interrupt Immediately if Scheduled Time In Past

76. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

77. Routable Interrupt Use case Interrupt on Button Timestamp An Event Some Crazy Interface We Didn’t Foresee If All Else Fails

78. Routable Interrupt Input Sources Routable – Digital Input Filter – Analog Trigger Latch Timestamp Wait for Acknowledge – Timestamp Will Not Change Until Acknowledge – Can be Disabled

79. FRC FPGA Subsystems Analog Input Oversample / Average Accumulator Analog Trigger Digital Input / Output Slow Digital Output Hobby PWM Output I 2 C Bus Digital Input Filtering Solenoid Output Watchdog Counter / Timer SPI Engine Time / Alarm Routable Interrupt Direct Memory Access

80. Direct Memory Access (DMA) Use case Data Streaming – FIR Filtering – Fourier Transform (Frequency Content) Snapshot of Sensor On Event – Position Observer

81. Direct Memory Access (DMA) Stream Data Directly to PPC Memory Sample Clock – Correlated Samples of Unrelated Data – Internally timed FPGA Clock Domain – Externally timed Routable Input Configurable Data Sources Sample Includes Timestamp Overrun Indication

82. Questions?