Presentation is loading. Please wait.

Presentation is loading. Please wait.

© intec 2002http://www.intec.rug.ac.be/groupsites/opto Fabrication Process Lithography Resist coating + soft bake Exposure Post-exposure bake + development.

Published byMildred Cameron Modified over 9 years ago

Similar presentations

Presentation on theme: "© intec 2002http://www.intec.rug.ac.be/groupsites/opto Fabrication Process Lithography Resist coating + soft bake Exposure Post-exposure bake + development."— Presentation transcript:

1 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Fabrication Process Lithography Resist coating + soft bake Exposure Post-exposure bake + development Etching Silicon etch Oxide Etch Post processing Dicing Substrate thinning Cleaving

2 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Si-substrate SiO 2 Si 205nm 400nm Step 1: Bare SOI wafer Layer structure 205 Top Si layer 400nm Buried Oxide Wafer size 8” (200mm)

3 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 2: Photoresist Coating Photoresist Resist Shipley UV3 800nm thick

4 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 3: Soft baking of resist Photoresist

5 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 4: Antireflective coating AR-coating AR coating No standing waves in resist during lithography 40nm of NFC

6 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 5: Illumination Deep UV Lithography Wavelength = 248nm NA = 0.63 Dose = 10-40 mJ Reduction = 4X

7 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 6: Post-exposure bake

8 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 7: Development

9 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 8: Silicon etch Etch properties TCP9400PTX ICP-RIE Low pressure /high density Cl 2 /HBr/He/O 2 chemistry Two-step break-through main etch

10 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 9: Oxide Etch Etch properties Exelan Dual frequency Medium pressure /medium density CF 4 /CHF 3 chemistry

11 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 10: Resist strip

12 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 11: Protective Resist Layer 750  m Substrate thinning = dangerous 1-3  m resist cover Wafer is diced into 3 x 3 cm 2 dies for substrate thinning

13 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Glass plate Bee’s wax Step 12: Glue on glass plate Glue = Bee’s wax Heated to ± 130°C

14 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Glass plate Bee’s wax Step 13: Substrate thinning 250  m Mechanical grinding Alumina powder 5-8 hours Remove 500  m

15 © intec 2002http://www.intec.rug.ac.be/groupsites/opto Step 14: Cleaning and Cleaving

Download ppt "© intec 2002http://www.intec.rug.ac.be/groupsites/opto Fabrication Process Lithography Resist coating + soft bake Exposure Post-exposure bake + development."

Similar presentations

Malaviya National Institute of Technology

Malaviya National Institute of Technology
FABRICATION PROCESSES

FABRICATION PROCESSES
CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
Advanced Manufacturing Choices

Advanced Manufacturing Choices
MetalMUMPs Process Flow

MetalMUMPs Process Flow
Fabrication pH Electrode Using Lift-Off Method and Electrodeposition Presented by Na Zhang.

Fabrication pH Electrode Using Lift-Off Method and Electrodeposition Presented by Na Zhang.
COUNCIL FOR THE CENTRAL LABORATORY OF THE RESEARCH COUNCILS EAP dimple fabrication process. Process D EAP dimple using carbon powder electrodes and DRIE.

COUNCIL FOR THE CENTRAL LABORATORY OF THE RESEARCH COUNCILS EAP dimple fabrication process. Process D EAP dimple using carbon powder electrodes and DRIE.
ECE/ChE 4752: Microelectronics Processing Laboratory

ECE/ChE 4752: Microelectronics Processing Laboratory
Lithography – Basic Concept

Lithography – Basic Concept
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.
Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: 10-20 Ω-cm Thickness: 505-545 µm.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
EE143 – Ali JaveySlide 5-1 Section 2: Lithography Jaeger Chapter 2 Litho Reader.

EE143 – Ali JaveySlide 5-1 Section 2: Lithography Jaeger Chapter 2 Litho Reader.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Wafer processing - I Clean room environment Semiconductor clean room: - controlled temperature (20ºC), air pressure, humidity (30%) - controlled airbone.

Wafer processing - I Clean room environment Semiconductor clean room: - controlled temperature (20ºC), air pressure, humidity (30%) - controlled airbone.
SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.

SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.
The Deposition Process

The Deposition Process
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

Similar presentations

Ads by Google